[PATCH] D92089: [PowerPC] Materialize i64 constants by enumerated patterns.

[Qing Shan Zhang via Phabricator via llvm-commits]

steven.zhang added a comment.

I see most of the benefit is from llvm/test/CodeGen/PowerPC/constants-i64.ll. Does the benefit come from the same pattern or several ? And you'd better visit all the f64 and compare the new algorithm with old to make sure that, there is no deg.



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Comment at: llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp:805
+static int findContiguousZerosAtLeast(uint64_t Imm, unsigned Num) {
+  assert((Num > 32 && Num < 64) && "Unexpected number.");
+  unsigned HiTZ = countTrailingZeros<uint32_t>(Hi_32(Imm));
----------------
So, why do we need this assertion ?


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Comment at: llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp:867
+                                    getI32Imm((Imm >> TZ) & 0xffff));
+    return CurDAG->getMachineNode(PPC::RLDIC, dl, MVT::i64, SDValue(Result, 0),
+                                  getI32Imm(TZ), getI32Imm(LZ));
----------------
You can use SLDI if the TZ and LZ meet some requirement.  A better idea is to fix it in InstAlias.


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Comment at: llvm/test/CodeGen/PowerPC/arr-fp-arg-no-copy.ll:15
+; CHECK-DAG: rldic 3, [[REG1]], 52, 2
+; CHECK-DAG: rldic 4, [[REG2]], 62, 1
 ; CHECK: bl xxx
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Some follow up to fix the missing instr aliasing for rldic -> sldi ?


Repository:
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  https://reviews.llvm.org/D92089/new/

https://reviews.llvm.org/D92089