[llvm] 40d1fb2 - [AArch64][GlobalISel] Swap select operands when inverting condition code

[Jessica Paquette via llvm-commits]

Author: Jessica Paquette
Date: 2020-12-08T14:17:26-08:00
New Revision: 40d1fb22293ba6409e802489ff106bbc95918565

URL: https://github.com/llvm/llvm-project/commit/40d1fb22293ba6409e802489ff106bbc95918565
DIFF: https://github.com/llvm/llvm-project/commit/40d1fb22293ba6409e802489ff106bbc95918565.diff

LOG: [AArch64][GlobalISel] Swap select operands when inverting condition code

This was not obvious when reading the imported tablegen patterns in
AArch64GenDAGISel.

Update select-select.mir.

Added: 
    

Modified: 
    llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
    llvm/test/CodeGen/AArch64/GlobalISel/select-select.mir

Removed: 
    


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diff  --git a/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp b/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
index 92da0be099f3..0834b0313453 100644
--- a/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
+++ b/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
@@ -1034,7 +1034,8 @@ AArch64InstructionSelector::emitSelect(Register Dst, Register True,
   unsigned Opc = Is32Bit ? AArch64::CSELWr : AArch64::CSELXr;
   bool Optimized = false;
   auto TryFoldBinOpIntoSelect = [&Opc, Is32Bit, &CC, &MRI,
-                                 &Optimized](Register &Reg, bool Invert) {
+                                 &Optimized](Register &Reg, Register &OtherReg,
+                                             bool Invert) {
     if (Optimized)
       return false;
 
@@ -1049,8 +1050,10 @@ AArch64InstructionSelector::emitSelect(Register Dst, Register True,
     if (mi_match(Reg, MRI, m_Neg(m_Reg(MatchReg)))) {
       Opc = Is32Bit ? AArch64::CSNEGWr : AArch64::CSNEGXr;
       Reg = MatchReg;
-      if (Invert)
+      if (Invert) {
         CC = AArch64CC::getInvertedCondCode(CC);
+        std::swap(Reg, OtherReg);
+      }
       return true;
     }
 
@@ -1064,8 +1067,10 @@ AArch64InstructionSelector::emitSelect(Register Dst, Register True,
     if (mi_match(Reg, MRI, m_Not(m_Reg(MatchReg)))) {
       Opc = Is32Bit ? AArch64::CSINVWr : AArch64::CSINVXr;
       Reg = MatchReg;
-      if (Invert)
+      if (Invert) {
         CC = AArch64CC::getInvertedCondCode(CC);
+        std::swap(Reg, OtherReg);
+      }
       return true;
     }
 
@@ -1079,8 +1084,10 @@ AArch64InstructionSelector::emitSelect(Register Dst, Register True,
     if (mi_match(Reg, MRI, m_GAdd(m_Reg(MatchReg), m_SpecificICst(1)))) {
       Opc = Is32Bit ? AArch64::CSINCWr : AArch64::CSINCXr;
       Reg = MatchReg;
-      if (Invert)
+      if (Invert) {
         CC = AArch64CC::getInvertedCondCode(CC);
+        std::swap(Reg, OtherReg);
+      }
       return true;
     }
 
@@ -1162,8 +1169,8 @@ AArch64InstructionSelector::emitSelect(Register Dst, Register True,
     return false;
   };
 
-  Optimized |= TryFoldBinOpIntoSelect(False, /*Invert = */ false);
-  Optimized |= TryFoldBinOpIntoSelect(True, /*Invert = */ true);
+  Optimized |= TryFoldBinOpIntoSelect(False, True, /*Invert = */ false);
+  Optimized |= TryFoldBinOpIntoSelect(True, False, /*Invert = */ true);
   Optimized |= TryOptSelectCst();
   auto SelectInst = MIB.buildInstr(Opc, {Dst}, {True, False}).addImm(CC);
   constrainSelectedInstRegOperands(*SelectInst, TII, TRI, RBI);

diff  --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-select.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-select.mir
index afc972cde3ee..9880d66f1070 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/select-select.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-select.mir
@@ -393,7 +393,7 @@ body:             |
     ; CHECK: %reg1:gpr32 = COPY $w1
     ; CHECK: %f:gpr32 = COPY $w2
     ; CHECK: [[ANDSWri:%[0-9]+]]:gpr32 = ANDSWri %reg0, 0, implicit-def $nzcv
-    ; CHECK: %select:gpr32 = CSNEGWr %reg1, %f, 0, implicit $nzcv
+    ; CHECK: %select:gpr32 = CSNEGWr %f, %reg1, 0, implicit $nzcv
     ; CHECK: $w0 = COPY %select
     ; CHECK: RET_ReallyLR implicit $w0
     %reg0:gpr(s32) = COPY $w0
@@ -514,7 +514,7 @@ body:             |
     ; CHECK: %reg1:gpr32 = COPY $w1
     ; CHECK: %f:gpr32 = COPY $w2
     ; CHECK: [[ANDSWri:%[0-9]+]]:gpr32 = ANDSWri %reg0, 0, implicit-def $nzcv
-    ; CHECK: %select:gpr32 = CSINVWr %reg1, %f, 0, implicit $nzcv
+    ; CHECK: %select:gpr32 = CSINVWr %f, %reg1, 0, implicit $nzcv
     ; CHECK: $w0 = COPY %select
     ; CHECK: RET_ReallyLR implicit $w0
     %reg0:gpr(s32) = COPY $w0
@@ -638,7 +638,7 @@ body:             |
     ; CHECK: %reg1:gpr32 = COPY $w1
     ; CHECK: %f:gpr32 = COPY $w2
     ; CHECK: [[ANDSWri:%[0-9]+]]:gpr32 = ANDSWri %reg0, 0, implicit-def $nzcv
-    ; CHECK: %select:gpr32 = CSINCWr %reg1, %f, 0, implicit $nzcv
+    ; CHECK: %select:gpr32 = CSINCWr %f, %reg1, 0, implicit $nzcv
     ; CHECK: $w0 = COPY %select
     ; CHECK: RET_ReallyLR implicit $w0
     %reg0:gpr(s32) = COPY $w0