[PATCH] D92812: [X86] AMD Znver3 (Family 19H) Enablement

Ganesh Gopalasubramanian via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Tue Dec 8 12:48:32 PST 2020

Previous message: [PATCH] D92812: [X86] AMD Znver3 (Family 19H) Enablement
Next message: [PATCH] D92813: [RISCV] Share VTYPE encoding code between the assembler and the CustomInserter for adding VSETVLI before vector instructions
Messages sorted by: [ date ] [ thread ] [ subject ] [ author ]

GGanesh added a comment.

In D92812#2439324 <https://reviews.llvm.org/D92812#2439324>, @RKSimon wrote:

> it looks like a very bad merge imo.

Yep, Thank you! I will post smaller incremental patches.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D92812/new/

https://reviews.llvm.org/D92812

Previous message: [PATCH] D92812: [X86] AMD Znver3 (Family 19H) Enablement
Next message: [PATCH] D92813: [RISCV] Share VTYPE encoding code between the assembler and the CustomInserter for adding VSETVLI before vector instructions
Messages sorted by: [ date ] [ thread ] [ subject ] [ author ]

More information about the llvm-commits mailing list