[PATCH] D92864: [PowerPC] Set SubRegIndex offset for sub_vsx1/sub_pair1
Jinsong Ji via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Tue Dec 8 10:15:12 PST 2020
jsji created this revision.
Herald added subscribers: shchenz, arphaman, kbarton, hiraditya, nemanjai.
jsji requested review of this revision.
Herald added a project: LLVM.
Herald added a subscriber: llvm-commits.
We defined SubRegIndex for 256/512 regs, but we did not set the offset for higher part,
so the offset of lower and higher part are the same.
This may cause problem in access ranges of SubReg, it is great that this haven't affected any testcases,
but I think we should fix it to avoid hidden bugs in the future.
You can see the changes in PPCGenRegisterInfo.inc.
@@ -637,25 +637,25 @@
extern const MCRegisterInfo::SubRegCoveredBits PPCSubRegIdxRanges[] = {
{ 65535, 65535 },
{ 0, 32 }, // sub_32
{ 0, 64 }, // sub_64
{ 2, 1 }, // sub_eq
{ 1, 1 }, // sub_gt
{ 0, 1 }, // sub_lt
{ 0, 256 }, // sub_pair0
- { 0, 256 }, // sub_pair1
+ { 256, 256 }, // sub_pair1
{ 3, 1 }, // sub_un
{ 0, 128 }, // sub_vsx0
- { 0, 128 }, // sub_vsx1
- { 0, 64 }, // sub_vsx1_then_sub_64
- { 0, 64 }, // sub_pair1_then_sub_64
- { 0, 128 }, // sub_pair1_then_sub_vsx0
- { 0, 128 }, // sub_pair1_then_sub_vsx1
- { 0, 64 }, // sub_pair1_then_sub_vsx1_then_sub_64
+ { 128, 128 }, // sub_vsx1
+ { 128, 64 }, // sub_vsx1_then_sub_64
+ { 256, 64 }, // sub_pair1_then_sub_64
+ { 256, 128 }, // sub_pair1_then_sub_vsx0
+ { 384, 128 }, // sub_pair1_then_sub_vsx1
+ { 384, 64 }, // sub_pair1_then_sub_vsx1_then_sub_64
};
Repository:
rG LLVM Github Monorepo
https://reviews.llvm.org/D92864
Files:
llvm/lib/Target/PowerPC/PPCRegisterInfo.td
Index: llvm/lib/Target/PowerPC/PPCRegisterInfo.td
===================================================================
--- llvm/lib/Target/PowerPC/PPCRegisterInfo.td
+++ llvm/lib/Target/PowerPC/PPCRegisterInfo.td
@@ -17,9 +17,9 @@
def sub_32 : SubRegIndex<32>;
def sub_64 : SubRegIndex<64>;
def sub_vsx0 : SubRegIndex<128>;
-def sub_vsx1 : SubRegIndex<128>;
+def sub_vsx1 : SubRegIndex<128, 128>;
def sub_pair0 : SubRegIndex<256>;
-def sub_pair1 : SubRegIndex<256>;
+def sub_pair1 : SubRegIndex<256, 256>;
}
-------------- next part --------------
A non-text attachment was scrubbed...
Name: D92864.310265.patch
Type: text/x-patch
Size: 516 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20201208/535b503b/attachment.bin>
More information about the llvm-commits
mailing list