[PATCH] D90020: [AArch64][SVE] Emit DWARF location expression for SVE stack objects.

[Jeremy Morse via Phabricator via llvm-commits]

jmorse added inline comments.


================
Comment at: llvm/test/CodeGen/AArch64/debug-info-sve-dbg-value.mir:9-10
+
+# CHECK0: : DW_OP_breg31 WSP+8)
+# CHECK0: DW_AT_type {{.*}}ty32
+#
----------------
sdesmalen wrote:
> jmorse wrote:
> > Could I suggest adding a larger DIExpression as the input to this check, for example an extra `DW_OP_uconst, 8, DW_OP_plus` just to ensure expression composition through your prependOffsetExpression implementation is covered in this test.
> > 
> > I'm assuming that the "*svint32_t" types act like aggregates in some way, and so can't have any other DWARF expression operators applied to them.
> > Could I suggest adding a larger DIExpression as the input to this check, for example an extra DW_OP_uconst, 8, DW_OP_plus just to ensure expression composition through your prependOffsetExpression implementation is covered in this test.
> Good suggestion, I've updated the test.
> 
> > I'm assuming that the "*svint32_t" types act like aggregates in some way, and so can't have any other DWARF expression operators applied to them.
> I think that's right, svint32_t are more or less opaque vector types. Do you have an example of expressions that would apply for regular (fixed-width) vectors?
> Do you have an example of expressions that would apply for regular (fixed-width) vectors?

Doing a quick search, I see a couple of examples:
  llvm/test/DebugInfo/MIR/ARM/split-superreg-complex.mir
  llvm/test/CodeGen/AMDGPU/debug-value.ll
that appear to apply non-trivial DIExpressions to fixed width vectors. Exactly how to interpret them is a bit beyond me alas, it may or may not be a concern with scalable vectors.


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  https://reviews.llvm.org/D90020/new/

https://reviews.llvm.org/D90020