[PATCH] D92842: [RFC][SelectionDAG] Add Target-Independent Compiler Barrier

[Sam Elliott via Phabricator via llvm-commits]

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While working on the RISC-V backend, we got bug reports from language frontends
that we were emitting instructions for compiler-only barriers: while emittiong
instructions wasn't incorrect in our case, it was inefficient, and contradicted
high-level language documentation which claimed that certain constructs (C++'s
`std::atomic_signal_fence`, C's `atomic_signal_fence`, Rust's
`compiler_barrier`) would not result in assembly instructions.

Many LLVM Target backends implement the same "MEMBARRIER" target-specific ISD
node to represent a compiler-only barrier, which we could have replicated in the
RISC-V backend, but I felt that it is now a reasonable time to have a
target-independent method for achieving the same, which backends can opt-in to
if they don't need to emit instructions.

It's not clear to me that all targets have strong enough memory models that this
should be applied across the board, but I've tried to implement it in a way that
backends can opt-in to using a target-independent barrier.

At the moment, I've modified the following backends to use the
target-independent barrier, to show how other backends could be updated:

- X86
- RISC-V
- Arm
- AArch64

I plan to write a short RFC for llvm-dev about this patch, as it has the
potential to affect many backends, including out-of-tree backends.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D92842

Files:
  llvm/include/llvm/CodeGen/MachineInstr.h
  llvm/include/llvm/Support/TargetOpcodes.def
  llvm/include/llvm/Target/Target.td
  llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
  llvm/lib/CodeGen/PatchableFunction.cpp
  llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
  llvm/lib/Target/AArch64/AArch64InstrAtomics.td
  llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp
  llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCCodeEmitter.cpp
  llvm/lib/Target/ARM/ARMInstrInfo.td
  llvm/lib/Target/ARM/ARMScheduleA57.td
  llvm/lib/Target/AVR/AVRInstrInfo.cpp
  llvm/lib/Target/MSP430/MSP430InstrInfo.cpp
  llvm/lib/Target/Mips/MipsInstrInfo.cpp
  llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
  llvm/lib/Target/RISCV/RISCVInstrInfo.td
  llvm/lib/Target/X86/X86ISelLowering.cpp
  llvm/lib/Target/X86/X86ISelLowering.h
  llvm/lib/Target/X86/X86InstrCompiler.td
  llvm/lib/Target/X86/X86InstrInfo.cpp
  llvm/lib/Target/X86/X86InstrInfo.td
  llvm/lib/Target/X86/X86MCInstLower.cpp
  llvm/test/CodeGen/AArch64/fence-singlethread.ll
  llvm/test/CodeGen/ARM/fence-singlethread.ll
  llvm/test/CodeGen/RISCV/atomic-fence.ll
  llvm/test/CodeGen/X86/atomic-idempotent.ll
  llvm/test/CodeGen/X86/atomic-unordered.ll
  llvm/test/CodeGen/X86/barrier-sse.ll
  llvm/test/CodeGen/X86/implicit-null-check.ll

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