[PATCH] D92841: [RISCV][NFC] Regenerate RISCV CodeGen tests

[Michael Munday via Phabricator via llvm-commits]

mundaym created this revision.
Herald added subscribers: frasercrmck, NickHung, evandro, luismarques, apazos, sameer.abuasal, pzheng, s.egerton, lenary, Jim, benna, psnobl, jocewei, PkmX, jfb, the_o, brucehoult, MartinMosbeck, rogfer01, edward-jones, zzheng, jrtc27, shiva0217, kito-cheng, niosHD, sabuasal, simoncook, johnrusso, rbar, asb, qcolombet.
mundaym requested review of this revision.
Herald added subscribers: llvm-commits, MaskRay.
Herald added a project: LLVM.

Regenerated using:

./llvm/utils/update_llc_test_checks.py -u llvm/test/CodeGen/RISCV/*.ll

This has added comments to spill-related instructions and added @plt to
some symbols.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D92841

Files:
  llvm/test/CodeGen/RISCV/alloca.ll
  llvm/test/CodeGen/RISCV/analyze-branch.ll
  llvm/test/CodeGen/RISCV/atomic-cmpxchg.ll
  llvm/test/CodeGen/RISCV/atomic-load-store.ll
  llvm/test/CodeGen/RISCV/atomic-rmw.ll
  llvm/test/CodeGen/RISCV/bswap-ctlz-cttz-ctpop.ll
  llvm/test/CodeGen/RISCV/byval.ll
  llvm/test/CodeGen/RISCV/callee-saved-fpr32s.ll
  llvm/test/CodeGen/RISCV/callee-saved-fpr64s.ll
  llvm/test/CodeGen/RISCV/callee-saved-gprs.ll
  llvm/test/CodeGen/RISCV/calling-conv-ilp32-ilp32f-common.ll
  llvm/test/CodeGen/RISCV/calling-conv-ilp32-ilp32f-ilp32d-common.ll
  llvm/test/CodeGen/RISCV/calling-conv-ilp32.ll
  llvm/test/CodeGen/RISCV/calling-conv-ilp32d.ll
  llvm/test/CodeGen/RISCV/calling-conv-ilp32f-ilp32d-common.ll
  llvm/test/CodeGen/RISCV/calling-conv-lp64-lp64f-common.ll
  llvm/test/CodeGen/RISCV/calling-conv-lp64-lp64f-lp64d-common.ll
  llvm/test/CodeGen/RISCV/calling-conv-lp64.ll
  llvm/test/CodeGen/RISCV/calling-conv-rv32f-ilp32.ll
  llvm/test/CodeGen/RISCV/calling-conv-sext-zext.ll
  llvm/test/CodeGen/RISCV/calls.ll
  llvm/test/CodeGen/RISCV/copysign-casts.ll
  llvm/test/CodeGen/RISCV/div.ll
  llvm/test/CodeGen/RISCV/double-br-fcmp.ll
  llvm/test/CodeGen/RISCV/double-calling-conv.ll
  llvm/test/CodeGen/RISCV/double-convert.ll
  llvm/test/CodeGen/RISCV/double-frem.ll
  llvm/test/CodeGen/RISCV/double-intrinsics.ll
  llvm/test/CodeGen/RISCV/double-mem.ll
  llvm/test/CodeGen/RISCV/double-previous-failure.ll
  llvm/test/CodeGen/RISCV/double-stack-spill-restore.ll
  llvm/test/CodeGen/RISCV/exception-pointer-register.ll
  llvm/test/CodeGen/RISCV/fastcc-float.ll
  llvm/test/CodeGen/RISCV/fastcc-int.ll
  llvm/test/CodeGen/RISCV/float-bit-preserving-dagcombines.ll
  llvm/test/CodeGen/RISCV/float-br-fcmp.ll
  llvm/test/CodeGen/RISCV/float-convert.ll
  llvm/test/CodeGen/RISCV/float-frem.ll
  llvm/test/CodeGen/RISCV/float-intrinsics.ll
  llvm/test/CodeGen/RISCV/float-mem.ll
  llvm/test/CodeGen/RISCV/fp128.ll
  llvm/test/CodeGen/RISCV/fp16-promote.ll
  llvm/test/CodeGen/RISCV/frame-info.ll
  llvm/test/CodeGen/RISCV/frame.ll
  llvm/test/CodeGen/RISCV/frameaddr-returnaddr.ll
  llvm/test/CodeGen/RISCV/ghccc-rv32.ll
  llvm/test/CodeGen/RISCV/ghccc-rv64.ll
  llvm/test/CodeGen/RISCV/half-bitmanip-dagcombines.ll
  llvm/test/CodeGen/RISCV/half-br-fcmp.ll
  llvm/test/CodeGen/RISCV/half-convert.ll
  llvm/test/CodeGen/RISCV/half-mem.ll
  llvm/test/CodeGen/RISCV/hoist-global-addr-base.ll
  llvm/test/CodeGen/RISCV/inline-asm-abi-names.ll
  llvm/test/CodeGen/RISCV/inline-asm-d-abi-names.ll
  llvm/test/CodeGen/RISCV/inline-asm-f-abi-names.ll
  llvm/test/CodeGen/RISCV/interrupt-attr-callee.ll
  llvm/test/CodeGen/RISCV/interrupt-attr-nocall.ll
  llvm/test/CodeGen/RISCV/interrupt-attr.ll
  llvm/test/CodeGen/RISCV/large-stack.ll
  llvm/test/CodeGen/RISCV/mul.ll
  llvm/test/CodeGen/RISCV/rem.ll
  llvm/test/CodeGen/RISCV/remat.ll
  llvm/test/CodeGen/RISCV/rv32Zbb.ll
  llvm/test/CodeGen/RISCV/rv32i-rv64i-float-double.ll
  llvm/test/CodeGen/RISCV/rv32i-rv64i-half.ll
  llvm/test/CodeGen/RISCV/rv64-large-stack.ll
  llvm/test/CodeGen/RISCV/rv64Zbb.ll
  llvm/test/CodeGen/RISCV/rv64i-complex-float.ll
  llvm/test/CodeGen/RISCV/rv64i-double-softfloat.ll
  llvm/test/CodeGen/RISCV/rv64i-single-softfloat.ll
  llvm/test/CodeGen/RISCV/select-and.ll
  llvm/test/CodeGen/RISCV/select-or.ll
  llvm/test/CodeGen/RISCV/shadowcallstack.ll
  llvm/test/CodeGen/RISCV/shifts.ll
  llvm/test/CodeGen/RISCV/shrinkwrap.ll
  llvm/test/CodeGen/RISCV/split-sp-adjust.ll
  llvm/test/CodeGen/RISCV/srem-lkk.ll
  llvm/test/CodeGen/RISCV/srem-vector-lkk.ll
  llvm/test/CodeGen/RISCV/stack-realignment-with-variable-sized-objects.ll
  llvm/test/CodeGen/RISCV/stack-realignment.ll
  llvm/test/CodeGen/RISCV/stack-store-check.ll
  llvm/test/CodeGen/RISCV/tls-models.ll
  llvm/test/CodeGen/RISCV/umulo-128-legalisation-lowering.ll
  llvm/test/CodeGen/RISCV/urem-lkk.ll
  llvm/test/CodeGen/RISCV/urem-vector-lkk.ll
  llvm/test/CodeGen/RISCV/vararg.ll