[PATCH] D91271: [AArch64] Attempt to sink mul operands

[Nicholas Guy via Phabricator via llvm-commits]

NickGuy added inline comments.


================
Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:10575
   }
+  case Instruction::Mul: {
+
----------------
resistor wrote:
> Why isn't this logic the same as for Add/Sub above?
>From my understanding, the Add/Sub above will only sink the operands if they are both extending/shuffling, while this case checks each operand individually.
It might be beneficial to make Add/Sub aware of this case, unifying the instruction cases, but that's not what this patch is trying to achieve (the parent patch that this aids only checks for mul patterns)


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  https://reviews.llvm.org/D91271/new/

https://reviews.llvm.org/D91271