[PATCH] D92823: [RISCV] Fix missing def operand when creating VSETVLI pseudos
Fraser Cormack via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Tue Dec 8 01:27:58 PST 2020
frasercrmck created this revision.
frasercrmck added reviewers: rogfer01, evandro, craig.topper, asb, lenary, luismarques, HsiangKai.
Herald added subscribers: NickHung, apazos, sameer.abuasal, pzheng, s.egerton, Jim, benna, psnobl, jocewei, PkmX, the_o, brucehoult, MartinMosbeck, edward-jones, zzheng, jrtc27, shiva0217, kito-cheng, niosHD, sabuasal, simoncook, johnrusso, rbar, hiraditya.
frasercrmck requested review of this revision.
Herald added subscribers: llvm-commits, MaskRay.
Herald added a project: LLVM.
The register operand was not being marked as a def when it should be. No tests
for this in the main branch as there are not yet any pseudos without a
non-negative VLIndex.
Also change the type of a virtual register operand from unsigned to Register
and adjust formatting.
Repository:
rG LLVM Github Monorepo
https://reviews.llvm.org/D92823
Files:
llvm/lib/Target/RISCV/RISCVISelLowering.cpp
Index: llvm/lib/Target/RISCV/RISCVISelLowering.cpp
===================================================================
--- llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -1955,13 +1955,13 @@
if (VLIndex >= 0) {
// Set VL (rs1 != X0).
- unsigned DestReg = MRI.createVirtualRegister(&RISCV::GPRRegClass);
+ Register DestReg = MRI.createVirtualRegister(&RISCV::GPRRegClass);
MIB.addReg(DestReg, RegState::Define | RegState::Dead)
- .addReg(MI.getOperand(VLIndex).getReg());
+ .addReg(MI.getOperand(VLIndex).getReg());
} else
// With no VL operator in the pseudo, do not modify VL (rd = X0, rs1 = X0).
- MIB.addReg(RISCV::X0, RegState::Dead)
- .addReg(RISCV::X0, RegState::Kill);
+ MIB.addReg(RISCV::X0, RegState::Define | RegState::Dead)
+ .addReg(RISCV::X0, RegState::Kill);
// For simplicity we reuse the vtype representation here.
// Bits | Name | Description
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