[PATCH] D91048: [AMDGPU] Add new pseudos for indirect addressing with VGPR Indexing
Stanislav Mekhanoshin via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Mon Dec 7 15:48:51 PST 2020
rampitec added inline comments.
================
Comment at: llvm/lib/Target/AMDGPU/SIInstructions.td:611
+ let VALU = 1;
+ let Uses = [M0, EXEC];
+}
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ruiling wrote:
> We may also need "let Defs = [M0];" here? as we are changing the bits of M0 registers.
> And what kind of benefit we can get through adding `M0` into `Uses`?
> We may also need "let Defs = [M0];" here? as we are changing the bits of M0 registers.
I think that's right, and MODE too, plus add MODE to uses. S_SET_GPR_IDX_ON defs and uses both.
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D91048/new/
https://reviews.llvm.org/D91048
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