[PATCH] D92793: [RISCV] Add (Proposed) Assembler Extend Pseudo-Instructions

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


================
Comment at: llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp:2324
+
+      emitToStreamer(Out, MCInstBuilder(RISCV::SLLI)
+                              .addOperand(DestReg)
----------------
This is indented too far


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Comment at: llvm/lib/Target/RISCV/RISCVInstrInfo.td:806
 
+def : InstAlias<"zext.b $rd, $rs", (ANDI GPR:$rd, GPR:$rs, 255)>;
+
----------------
We two identical InstAliases to this in RISCVInstrInfoB.td when Zbb is enabled. Those can be removed now.


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Comment at: llvm/lib/Target/RISCV/RISCVInstrInfo.td:1055
+
+let hasSideEffects = 0, mayLoad = 0, mayStore = 0, isCodeGenOnly = 0,
+    isAsmParserOnly = 1 in {
----------------
What happens when the Zbb extension is enabled? Do its InstAliases have priority?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D92793/new/

https://reviews.llvm.org/D92793