[PATCH] D92420: [PowerPC] Exploitation of xxeval instruction for AND and NAND

[Jinsong Ji via Phabricator via llvm-commits]

jsji added inline comments.


================
Comment at: llvm/lib/Target/PowerPC/PPCInstrPrefix.td:2584
+  // and(A, B, C)
+  def : xxevalPattern<(and v4i32:$vA, (and v4i32:$vB, v4i32:$vC)), 1>;
+  // and(A, xor(B, C))
----------------
stefanp wrote:
> jsji wrote:
> > Can we  use switch table + foreach to define all patterns?
> > 
> > something like:
> > 
> > ```
> > class xxevalpat<bits<8> imm>{                                                                                                                                                 
> > dag pattern = !cond(!eq(imm,  1): (and v4i32:$vA, (and v4i32:$vB, v4i32:$vC)),                                                                                                                  
> >                         !eq(imm,  6): (and v4i32:$vA, (xor v4i32:$vB, v4i32:$vC))   
> > ...                                                                                                            );                                                                                                                                                        }             
> > 
> > 
> >   foreach i = [1,6...] in {               
> >          def : xxevalPattern< xxevalpat<i>.pattern, i>;                                                                                                                            }       
> >   }
> > ```
> > 
> Hmm... I actually feel like this would make things more confusing to read.
> It is another level of indirection but in the end I am still just listing pairs of immediate values and patterns that go with them. On top of that I would have to maintain a list of values in the `foreach`. 
> I think I prefer to leave this as it stands.
> I would have to maintain a list of values in the foreach

I think we don't, we may simple foreach 1-255, then handle the values in class.

>  but in the end I am still just listing pairs of immediate values and patterns that go with them.

This is just the implementation example, I was hoping that we can come up with better code that can return the pattern according to bit of imm.

But yeah, this is nice to have.



================
Comment at: llvm/lib/Target/PowerPC/PPCInstrPrefix.td:2569
+
 let AddedComplexity = 400, Predicates = [PrefixInstrs] in {
  def : Pat<(v4i32 (build_vector i32immNonAllOneNonZero:$A,
----------------
stefanp wrote:
> jsji wrote:
> > Why `xxeval` needs `PrefixInstrs` Predicates?
> It is required because `xxeval` is a 64 bit prefixed instruction.
Ah.. OK.  Missed that in ISA.. 


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https://reviews.llvm.org/D92420