[PATCH] D92767: [AMDGPU] Resolve issues when picking between ds_read/write and ds_read2/write2

[Mirko Brkusanin via Phabricator via llvm-commits]

mbrkusanin created this revision.
mbrkusanin added reviewers: foad, arsenm.
mbrkusanin added a project: LLVM.
Herald added subscribers: kerbowa, hiraditya, t-tye, tpr, dstuttard, yaxunl, nhaehnle, jvesely, kzhuravl.
mbrkusanin requested review of this revision.
Herald added a subscriber: wdng.

Both ds_read_b128 and ds_read2_b64 are valid for 128bit 16-byte aligned 
loads but the one that will be selected is determined either by the order in
tablegen or by the AddedComplexity attribute. Currently ds_read_b128 has
priority.

While ds_read2_b64 has lower alignment requirements, we cannot always 
restrict ds_read_b128 to 16-byte alignment because of unaligned-access-mode
option. This was causing ds_read_b128 to be selected for 8-byte aligned
loads regardles of chosen access mode.

To resolve this we use two patterns for selecting ds_read_b128. One
requires alignment of 16-byte and the other requires 
unaligned-access-mode option.

Same goes for ds_write2_b64 and ds_write_b128.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D92767

Files:
  llvm/lib/Target/AMDGPU/AMDGPU.td
  llvm/lib/Target/AMDGPU/DSInstructions.td
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-local-128.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/lds-misaligned-bug.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/load-local.128.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/store-local.128.ll
  llvm/test/CodeGen/AMDGPU/lds-misaligned-bug.ll
  llvm/test/CodeGen/AMDGPU/load-local.128.ll
  llvm/test/CodeGen/AMDGPU/store-local.128.ll

-------------- next part --------------
A non-text attachment was scrubbed...
Name: D92767.309917.patch
Type: text/x-patch
Size: 14175 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20201207/cf096bcf/attachment.bin>