[PATCH] D91048: [AMDGPU] Add new pseudos for indirect addressing with VGPR Indexing

[Ruiling, Song via Phabricator via llvm-commits]

ruiling added a comment.

The idea of the patch looks good to me. I went through the patch, didn't see other issues than the inline comments. But I do hope more experienced guy take further look. Thanks for working on this as we also meet the issue that TwoAddressInstruction pass inserts COPY inside the s_set_gpr_idx_on/off instructions and generate mis-compiled shader. So we really depends on this patch to fix the issue.



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Comment at: llvm/lib/Target/AMDGPU/SIInstructions.td:611
+  let VALU = 1;
+  let Uses = [M0, EXEC];
+}
----------------
We may also need "let Defs = [M0];" here? as we are changing the bits of M0 registers.
And what kind of benefit we can get through adding `M0` into `Uses`?


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Comment at: llvm/lib/Target/AMDGPU/SIInstructions.td:626
+  let VALU = 1;
+  let Uses = [M0, EXEC];
+}
----------------
and also here?


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D91048/new/

https://reviews.llvm.org/D91048