[PATCH] D89449: [RISCV] Initial infrastructure for code generation of the RISC-V V-extension

Thu Dec 3 10:57:27 PST 2020

craig.topper added a comment.

In D89449#2430454 <https://reviews.llvm.org/D89449#2430454>, @frasercrmck wrote:

> In D89449#2430127 <https://reviews.llvm.org/D89449#2430127>, @craig.topper wrote:
>
>> Does anyone have any additional feedback on this patch or the direction? @evandro should be providing a patch to show how intrinsics will work soon.
>
> I'm generally happy with this approach; I've been using it downstream to support fixed-length vectors with success.
>
> I think there was your outstanding question about the pseudos "using" `VL` and `VTYPE` immediately after ISel, and there's the idea you brought up in D92228 <https://reviews.llvm.org/D92228> about duplicating the pseudos for masked and unmasked operations. I think it'd be good to come to some kind of agreement on those, but I'm also happy for them to be deferred until later. I don't think either affect the "correctness" of this patch.

I'm hoping the VL/VTYPE uses don't cause a problem as I don't know how to make InstrEmitter fix it. It looks like the VE target is also marking their instructions as using their VL register and don't insert LVL instructions until very late in the pipeline.

I don't know if we're going to have an answer for the masked/unmasked soon. I think we might just use earlyclobber in the initial patches and suffer the bad register allocation so we can make forward progress.

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