[PATCH] D88569: [DAGCombiner] Call SimplifyDemandedBits to simplify EXTRACT_VECTOR_ELT

[Bing Yu via Phabricator via llvm-commits]

yubing added inline comments.


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Comment at: llvm/test/CodeGen/X86/vector-fshr-128.ll:188-189
 ; X32-SSE-NEXT:    psrlq %xmm4, %xmm5
-; X32-SSE-NEXT:    pshufd {{.*#+}} xmm4 = xmm4[2,3,2,3]
+; X32-SSE-NEXT:    pxor %xmm6, %xmm6
+; X32-SSE-NEXT:    punpckhdq {{.*#+}} xmm4 = xmm4[2],xmm6[2],xmm4[3],xmm6[3]
 ; X32-SSE-NEXT:    psrlq %xmm4, %xmm1
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Hi, during combination before legalizeDAG. there are the following Nodes:
              t63: i32 = extract_vector_elt t62, Constant:i32<2>
              t64: i32 = extract_vector_elt t62, Constant:i32<3>
            t66: v4i32 = BUILD_VECTOR t63, t64, undef:i32, undef:i32
SimplifyDemandedBits deduce that t64 is a zero, so t66 will transformed into a pxor and a punpckhqd instead of a single pshufd. 

Maybe in such a case where a buildvector have elts which are extracted from the same vector, you shouldn't SimplifyDemandedBits for extract_vector_elt. 


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D88569/new/

https://reviews.llvm.org/D88569