[PATCH] D91416: [VE] LVLGen sets VL before vector insts

Fri Dec 4 23:58:14 PST 2020

kaz7 added a comment.

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Comment at: llvm/lib/Target/VE/LVLGen.cpp:92
+      // Old VL is overwritten, so disable HasRegForVL.
+      if (MI->findRegisterDefOperandIdx(RegForVL, false, false, TRI) != -1) {
+        LLVM_DEBUG(dbgs() << RegName(RegForVL) << " is killed: ");
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kaz7 wrote:
> craig.topper wrote:
> > Does this handle the case of a call in the middle of a group of vector instructions? Such a call might modify VL. But I don't think the call will show VL as a def for findRegisterDefOperandIdx.
> No, this doesn't handle such case and generates wrong instructions.  Thank you for suggestions.  I'll prepare updates.
@craig.topper, thank you for your suggestion.  I fixed the problem in D92716.  Please check it out when you have time.  Thanks!

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https://reviews.llvm.org/D91416