[PATCH] D92707: [AArch64][GlobalISel] Narrow 128-bit regs to 64-bit regs in emitTestBit

[Jessica Paquette via Phabricator via llvm-commits]

paquette created this revision.
paquette added a reviewer: aemerson.
Herald added subscribers: danielkiss, hiraditya, kristof.beyls, rovka.
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Herald added a project: LLVM.

When we have a 128-bit register, `emitTestBit` would incorrectly narrow to 32 bits always. If the bit number was > 32, then we would need a TB(N)ZX. This would cause a crash, as we'd have the wrong register class. (PR48379)

This generalizes `narrowExtReg` into `narrowOrWidenScalarIfNeeded`.

This also allows us to remove `widenGPRBankRegIfNeeded` entirely, since `selectCopy` correctly handles SUBREG_TO_REG etc.

This does create some codegen changes (since `selectCopy` uses the `all` regclass variants). However, I think that these will likely be optimized away, and we can always improve the `selectCopy` code.


https://reviews.llvm.org/D92707

Files:
  llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
  llvm/test/CodeGen/AArch64/GlobalISel/opt-fold-ext-tbz-tbnz.mir
  llvm/test/CodeGen/AArch64/GlobalISel/subreg-copy.mir
  llvm/test/CodeGen/AArch64/GlobalISel/widen-narrow-tbz-tbnz.mir

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