[PATCH] D92420: [PowerPC] Exploitation of xxeval instruction for AND and NAND

[Jinsong Ji via Phabricator via llvm-commits]

jsji added inline comments.


================
Comment at: llvm/lib/Target/PowerPC/PPCInstrPrefix.td:2584
+  // and(A, B, C)
+  def : xxevalPattern<(and v4i32:$vA, (and v4i32:$vB, v4i32:$vC)), 1>;
+  // and(A, xor(B, C))
----------------
Can we  use switch table + foreach to define all patterns?

something like:

```
class xxevalpat<bits<8> imm>{                                                                                                                                                 
dag pattern = !cond(!eq(imm,  1): (and v4i32:$vA, (and v4i32:$vB, v4i32:$vC)),                                                                                                                  
                        !eq(imm,  6): (and v4i32:$vA, (xor v4i32:$vB, v4i32:$vC))   
...                                                                                                            );                                                                                                                                                        }             


  foreach i = [1,6...] in {               
         def : xxevalPattern< xxevalpat<i>.pattern, i>;                                                                                                                            }       
  }
```



================
Comment at: llvm/lib/Target/PowerPC/PPCInstrPrefix.td:2569
+
 let AddedComplexity = 400, Predicates = [PrefixInstrs] in {
  def : Pat<(v4i32 (build_vector i32immNonAllOneNonZero:$A,
----------------
Why `xxeval` needs `PrefixInstrs` Predicates?


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D92420/new/

https://reviews.llvm.org/D92420