[PATCH] D92296: [AARCH64] Improve accumulator forwarding for Cortex-A57 model

[Dave Green via Phabricator via llvm-commits]

dmgreen added a reviewer: evgeny777.
dmgreen added a comment.

Is it possible to add an llvm-mca test for the instructions that change here? Preferably showing all the instructions that are touched. If not an mir level test might be simple way to create some tests along the same lines (although there's nothing very wrong with the ll test you have, an mir test can be more targeted).



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Comment at: llvm/lib/Target/AArch64/AArch64SchedA57.td:96
 def : SchedAlias<WriteFImm,  A57Write_3cyc_1V>;
-def : SchedAlias<WriteFMul,  A57Write_5cyc_1V>;
+// Replacing SchedAlias with WriteRes for advance lookup
+def : WriteRes<WriteFMul, [A57UnitV]> { let Latency = 5;}
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Can you update this comment to why this is different, not why it has _changed_ (which doesn't mean a lot once the code is in-tree.)

So something like "Use a WriteRes as opposed to SchedAlias for advance lookup"


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Comment at: llvm/lib/Target/AArch64/AArch64SchedA57.td:419
+// ASIMD shift by register, basic, D-form
+def : InstRW<[A57Write_3cyc_1X_NonMul_Forward], (instregex "^[SU]SHL(v1i8|v1i16|v1i32|v1i64|v8i8|v4i16|v2i32|b|d|h|s)")>;
 
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What is a ^[SU]SHLv1i8 ?
Same for all these others.


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Comment at: llvm/lib/Target/AArch64/AArch64SchedA57WriteRes.td:54
 def A57Write_4cyc_1L  : SchedWriteRes<[A57UnitL]> { let Latency = 4;  }
+def A57Write_4cyc_1I  : SchedWriteRes<[A57UnitI]> { let Latency = 4;  }
 def A57Write_4cyc_1X  : SchedWriteRes<[A57UnitX]> { let Latency = 4;  }
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Where is this used?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D92296/new/

https://reviews.llvm.org/D92296