[PATCH] D92228: [RISCV] Add MIR tests exposing missed InstAliases

[ShihPo Hung via Phabricator via llvm-commits]

arcbbb added a comment.



In D92228#2424007 <https://reviews.llvm.org/D92228#2424007>, @rogfer01 wrote:

> 2. Regarding `@earlyclobber`, yes it is not ideal as it is now. But it doesn't only impact masking (though perhaps that is the clearest case).
>
> Unless the ISA has changed (and I admit I might be a bit outdated here) my understanding is that we still have cases where `@earlyclobber` will be needed and it will still fall short.
>
> For instance, mixed widenings such as `vwadd.wv` are complex to model because iirc an instruction like `vwadd.wv v2, v2, v1` is fine while `vwadd.wv v2, v2, v3` is not. I understand that using `@earlyclobber` a thing like `vwadd.wv v4, v2, v1` is the best we can get.
>
> I asked about this here http://lists.llvm.org/pipermail/llvm-dev/2020-May/141383.html

Thank you for the sharing, @rogfer01.
This is a good case that shows I cannot get an ideal RA by just duplicating a set of masked/unmasked pseudos.
In this `vwadd.wv` case,

  ; Assume LMUL=M1, EMUL=M2
  ; Widening signed integer add, 2*SEW = 2*SEW +/- SEW
  vwadd.wv  {v2,v3}, {v2 v3}, v4 ; valid: vd eew == vs2 eew
  vwadd.wv  {v4,v5}, {v2 v3}, v5 ; valid: vd eew > vs1 eew, overlap is in the highest-numbered part.
  vwadd.wv  {v4,v5}, {v2 v3}, v4 ; invalid

A register class constraint still falls short for this.


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