[llvm] b912381 - [VE] Add veqv and vseq intrinsic instructions
Kazushi Marukawa via llvm-commits
llvm-commits at lists.llvm.org
Thu Dec 3 00:39:33 PST 2020
Author: Kazushi (Jam) Marukawa
Date: 2020-12-03T17:39:24+09:00
New Revision: b91238173dd9ef84a78c77c099cc26f934443a05
URL: https://github.com/llvm/llvm-project/commit/b91238173dd9ef84a78c77c099cc26f934443a05
DIFF: https://github.com/llvm/llvm-project/commit/b91238173dd9ef84a78c77c099cc26f934443a05.diff
LOG: [VE] Add veqv and vseq intrinsic instructions
Add veqv and vseq intrinsic instructions and regression tests.
Reviewed By: simoll
Differential Revision: https://reviews.llvm.org/D92527
Added:
llvm/test/CodeGen/VE/VELIntrinsics/veqv.ll
llvm/test/CodeGen/VE/VELIntrinsics/vseq.ll
Modified:
llvm/include/llvm/IR/IntrinsicsVEVL.gen.td
llvm/lib/Target/VE/VEInstrIntrinsicVL.gen.td
Removed:
################################################################################
diff --git a/llvm/include/llvm/IR/IntrinsicsVEVL.gen.td b/llvm/include/llvm/IR/IntrinsicsVEVL.gen.td
index 7c3b523b16b4..116cdc6fcc6a 100644
--- a/llvm/include/llvm/IR/IntrinsicsVEVL.gen.td
+++ b/llvm/include/llvm/IR/IntrinsicsVEVL.gen.td
@@ -395,3 +395,23 @@ let TargetPrefix = "ve" in def int_ve_vl_pvxor_vsvl : GCCBuiltin<"__builtin_ve_v
let TargetPrefix = "ve" in def int_ve_vl_pvxor_vsvvl : GCCBuiltin<"__builtin_ve_vl_pvxor_vsvvl">, Intrinsic<[LLVMType<v256f64>], [LLVMType<i64>, LLVMType<v256f64>, LLVMType<v256f64>, LLVMType<i32>], [IntrNoMem]>;
let TargetPrefix = "ve" in def int_ve_vl_pvxor_vvvMvl : GCCBuiltin<"__builtin_ve_vl_pvxor_vvvMvl">, Intrinsic<[LLVMType<v256f64>], [LLVMType<v256f64>, LLVMType<v256f64>, LLVMType<v512i1>, LLVMType<v256f64>, LLVMType<i32>], [IntrNoMem]>;
let TargetPrefix = "ve" in def int_ve_vl_pvxor_vsvMvl : GCCBuiltin<"__builtin_ve_vl_pvxor_vsvMvl">, Intrinsic<[LLVMType<v256f64>], [LLVMType<i64>, LLVMType<v256f64>, LLVMType<v512i1>, LLVMType<v256f64>, LLVMType<i32>], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_veqv_vvvl : GCCBuiltin<"__builtin_ve_vl_veqv_vvvl">, Intrinsic<[LLVMType<v256f64>], [LLVMType<v256f64>, LLVMType<v256f64>, LLVMType<i32>], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_veqv_vvvvl : GCCBuiltin<"__builtin_ve_vl_veqv_vvvvl">, Intrinsic<[LLVMType<v256f64>], [LLVMType<v256f64>, LLVMType<v256f64>, LLVMType<v256f64>, LLVMType<i32>], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_veqv_vsvl : GCCBuiltin<"__builtin_ve_vl_veqv_vsvl">, Intrinsic<[LLVMType<v256f64>], [LLVMType<i64>, LLVMType<v256f64>, LLVMType<i32>], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_veqv_vsvvl : GCCBuiltin<"__builtin_ve_vl_veqv_vsvvl">, Intrinsic<[LLVMType<v256f64>], [LLVMType<i64>, LLVMType<v256f64>, LLVMType<v256f64>, LLVMType<i32>], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_veqv_vvvmvl : GCCBuiltin<"__builtin_ve_vl_veqv_vvvmvl">, Intrinsic<[LLVMType<v256f64>], [LLVMType<v256f64>, LLVMType<v256f64>, LLVMType<v256i1>, LLVMType<v256f64>, LLVMType<i32>], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_veqv_vsvmvl : GCCBuiltin<"__builtin_ve_vl_veqv_vsvmvl">, Intrinsic<[LLVMType<v256f64>], [LLVMType<i64>, LLVMType<v256f64>, LLVMType<v256i1>, LLVMType<v256f64>, LLVMType<i32>], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_pveqv_vvvl : GCCBuiltin<"__builtin_ve_vl_pveqv_vvvl">, Intrinsic<[LLVMType<v256f64>], [LLVMType<v256f64>, LLVMType<v256f64>, LLVMType<i32>], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_pveqv_vvvvl : GCCBuiltin<"__builtin_ve_vl_pveqv_vvvvl">, Intrinsic<[LLVMType<v256f64>], [LLVMType<v256f64>, LLVMType<v256f64>, LLVMType<v256f64>, LLVMType<i32>], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_pveqv_vsvl : GCCBuiltin<"__builtin_ve_vl_pveqv_vsvl">, Intrinsic<[LLVMType<v256f64>], [LLVMType<i64>, LLVMType<v256f64>, LLVMType<i32>], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_pveqv_vsvvl : GCCBuiltin<"__builtin_ve_vl_pveqv_vsvvl">, Intrinsic<[LLVMType<v256f64>], [LLVMType<i64>, LLVMType<v256f64>, LLVMType<v256f64>, LLVMType<i32>], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_pveqv_vvvMvl : GCCBuiltin<"__builtin_ve_vl_pveqv_vvvMvl">, Intrinsic<[LLVMType<v256f64>], [LLVMType<v256f64>, LLVMType<v256f64>, LLVMType<v512i1>, LLVMType<v256f64>, LLVMType<i32>], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_pveqv_vsvMvl : GCCBuiltin<"__builtin_ve_vl_pveqv_vsvMvl">, Intrinsic<[LLVMType<v256f64>], [LLVMType<i64>, LLVMType<v256f64>, LLVMType<v512i1>, LLVMType<v256f64>, LLVMType<i32>], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_vseq_vl : GCCBuiltin<"__builtin_ve_vl_vseq_vl">, Intrinsic<[LLVMType<v256f64>], [LLVMType<i32>], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_vseq_vvl : GCCBuiltin<"__builtin_ve_vl_vseq_vvl">, Intrinsic<[LLVMType<v256f64>], [LLVMType<v256f64>, LLVMType<i32>], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_pvseqlo_vl : GCCBuiltin<"__builtin_ve_vl_pvseqlo_vl">, Intrinsic<[LLVMType<v256f64>], [LLVMType<i32>], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_pvseqlo_vvl : GCCBuiltin<"__builtin_ve_vl_pvseqlo_vvl">, Intrinsic<[LLVMType<v256f64>], [LLVMType<v256f64>, LLVMType<i32>], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_pvsequp_vl : GCCBuiltin<"__builtin_ve_vl_pvsequp_vl">, Intrinsic<[LLVMType<v256f64>], [LLVMType<i32>], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_pvsequp_vvl : GCCBuiltin<"__builtin_ve_vl_pvsequp_vvl">, Intrinsic<[LLVMType<v256f64>], [LLVMType<v256f64>, LLVMType<i32>], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_pvseq_vl : GCCBuiltin<"__builtin_ve_vl_pvseq_vl">, Intrinsic<[LLVMType<v256f64>], [LLVMType<i32>], [IntrNoMem]>;
+let TargetPrefix = "ve" in def int_ve_vl_pvseq_vvl : GCCBuiltin<"__builtin_ve_vl_pvseq_vvl">, Intrinsic<[LLVMType<v256f64>], [LLVMType<v256f64>, LLVMType<i32>], [IntrNoMem]>;
diff --git a/llvm/lib/Target/VE/VEInstrIntrinsicVL.gen.td b/llvm/lib/Target/VE/VEInstrIntrinsicVL.gen.td
index cfe2c31f5a6f..a2ca074d655b 100644
--- a/llvm/lib/Target/VE/VEInstrIntrinsicVL.gen.td
+++ b/llvm/lib/Target/VE/VEInstrIntrinsicVL.gen.td
@@ -589,3 +589,23 @@ def : Pat<(int_ve_vl_pvxor_vsvl i64:$sy, v256f64:$vz, i32:$vl), (PVXORrvl i64:$s
def : Pat<(int_ve_vl_pvxor_vsvvl i64:$sy, v256f64:$vz, v256f64:$pt, i32:$vl), (PVXORrvl_v i64:$sy, v256f64:$vz, i32:$vl, v256f64:$pt)>;
def : Pat<(int_ve_vl_pvxor_vvvMvl v256f64:$vy, v256f64:$vz, v512i1:$vm, v256f64:$pt, i32:$vl), (PVXORvvml_v v256f64:$vy, v256f64:$vz, v512i1:$vm, i32:$vl, v256f64:$pt)>;
def : Pat<(int_ve_vl_pvxor_vsvMvl i64:$sy, v256f64:$vz, v512i1:$vm, v256f64:$pt, i32:$vl), (PVXORrvml_v i64:$sy, v256f64:$vz, v512i1:$vm, i32:$vl, v256f64:$pt)>;
+def : Pat<(int_ve_vl_veqv_vvvl v256f64:$vy, v256f64:$vz, i32:$vl), (VEQVvvl v256f64:$vy, v256f64:$vz, i32:$vl)>;
+def : Pat<(int_ve_vl_veqv_vvvvl v256f64:$vy, v256f64:$vz, v256f64:$pt, i32:$vl), (VEQVvvl_v v256f64:$vy, v256f64:$vz, i32:$vl, v256f64:$pt)>;
+def : Pat<(int_ve_vl_veqv_vsvl i64:$sy, v256f64:$vz, i32:$vl), (VEQVrvl i64:$sy, v256f64:$vz, i32:$vl)>;
+def : Pat<(int_ve_vl_veqv_vsvvl i64:$sy, v256f64:$vz, v256f64:$pt, i32:$vl), (VEQVrvl_v i64:$sy, v256f64:$vz, i32:$vl, v256f64:$pt)>;
+def : Pat<(int_ve_vl_veqv_vvvmvl v256f64:$vy, v256f64:$vz, v256i1:$vm, v256f64:$pt, i32:$vl), (VEQVvvml_v v256f64:$vy, v256f64:$vz, v256i1:$vm, i32:$vl, v256f64:$pt)>;
+def : Pat<(int_ve_vl_veqv_vsvmvl i64:$sy, v256f64:$vz, v256i1:$vm, v256f64:$pt, i32:$vl), (VEQVrvml_v i64:$sy, v256f64:$vz, v256i1:$vm, i32:$vl, v256f64:$pt)>;
+def : Pat<(int_ve_vl_pveqv_vvvl v256f64:$vy, v256f64:$vz, i32:$vl), (PVEQVvvl v256f64:$vy, v256f64:$vz, i32:$vl)>;
+def : Pat<(int_ve_vl_pveqv_vvvvl v256f64:$vy, v256f64:$vz, v256f64:$pt, i32:$vl), (PVEQVvvl_v v256f64:$vy, v256f64:$vz, i32:$vl, v256f64:$pt)>;
+def : Pat<(int_ve_vl_pveqv_vsvl i64:$sy, v256f64:$vz, i32:$vl), (PVEQVrvl i64:$sy, v256f64:$vz, i32:$vl)>;
+def : Pat<(int_ve_vl_pveqv_vsvvl i64:$sy, v256f64:$vz, v256f64:$pt, i32:$vl), (PVEQVrvl_v i64:$sy, v256f64:$vz, i32:$vl, v256f64:$pt)>;
+def : Pat<(int_ve_vl_pveqv_vvvMvl v256f64:$vy, v256f64:$vz, v512i1:$vm, v256f64:$pt, i32:$vl), (PVEQVvvml_v v256f64:$vy, v256f64:$vz, v512i1:$vm, i32:$vl, v256f64:$pt)>;
+def : Pat<(int_ve_vl_pveqv_vsvMvl i64:$sy, v256f64:$vz, v512i1:$vm, v256f64:$pt, i32:$vl), (PVEQVrvml_v i64:$sy, v256f64:$vz, v512i1:$vm, i32:$vl, v256f64:$pt)>;
+def : Pat<(int_ve_vl_vseq_vl i32:$vl), (VSEQl i32:$vl)>;
+def : Pat<(int_ve_vl_vseq_vvl v256f64:$pt, i32:$vl), (VSEQl_v i32:$vl, v256f64:$pt)>;
+def : Pat<(int_ve_vl_pvseqlo_vl i32:$vl), (PVSEQLOl i32:$vl)>;
+def : Pat<(int_ve_vl_pvseqlo_vvl v256f64:$pt, i32:$vl), (PVSEQLOl_v i32:$vl, v256f64:$pt)>;
+def : Pat<(int_ve_vl_pvsequp_vl i32:$vl), (PVSEQUPl i32:$vl)>;
+def : Pat<(int_ve_vl_pvsequp_vvl v256f64:$pt, i32:$vl), (PVSEQUPl_v i32:$vl, v256f64:$pt)>;
+def : Pat<(int_ve_vl_pvseq_vl i32:$vl), (PVSEQl i32:$vl)>;
+def : Pat<(int_ve_vl_pvseq_vvl v256f64:$pt, i32:$vl), (PVSEQl_v i32:$vl, v256f64:$pt)>;
diff --git a/llvm/test/CodeGen/VE/VELIntrinsics/veqv.ll b/llvm/test/CodeGen/VE/VELIntrinsics/veqv.ll
new file mode 100644
index 000000000000..058ccde6956b
--- /dev/null
+++ b/llvm/test/CodeGen/VE/VELIntrinsics/veqv.ll
@@ -0,0 +1,212 @@
+; RUN: llc < %s -mtriple=ve -mattr=+vpu | FileCheck %s
+
+;;; Test vector equivalence intrinsic instructions
+;;;
+;;; Note:
+;;; We test VEQV*vvl, VEQV*vvl_v, VEQV*rvl, VEQV*rvl_v, VEQV*vvml_v,
+;;; VEQV*rvml_v, PVEQV*vvl, PVEQV*vvl_v, PVEQV*rvl, PVEQV*rvl_v, PVEQV*vvml_v,
+;;; and PVEQV*rvml_v instructions.
+
+; Function Attrs: nounwind readnone
+define fastcc <256 x double> @veqv_vvvl(<256 x double> %0, <256 x double> %1) {
+; CHECK-LABEL: veqv_vvvl:
+; CHECK: # %bb.0:
+; CHECK-NEXT: lea %s0, 256
+; CHECK-NEXT: lvl %s0
+; CHECK-NEXT: veqv %v0, %v0, %v1
+; CHECK-NEXT: b.l.t (, %s10)
+ %3 = tail call fast <256 x double> @llvm.ve.vl.veqv.vvvl(<256 x double> %0, <256 x double> %1, i32 256)
+ ret <256 x double> %3
+}
+
+; Function Attrs: nounwind readnone
+declare <256 x double> @llvm.ve.vl.veqv.vvvl(<256 x double>, <256 x double>, i32)
+
+; Function Attrs: nounwind readnone
+define fastcc <256 x double> @veqv_vvvvl(<256 x double> %0, <256 x double> %1, <256 x double> %2) {
+; CHECK-LABEL: veqv_vvvvl:
+; CHECK: # %bb.0:
+; CHECK-NEXT: lea %s0, 128
+; CHECK-NEXT: lvl %s0
+; CHECK-NEXT: veqv %v2, %v0, %v1
+; CHECK-NEXT: lea %s16, 256
+; CHECK-NEXT: lvl %s16
+; CHECK-NEXT: vor %v0, (0)1, %v2
+; CHECK-NEXT: b.l.t (, %s10)
+ %4 = tail call fast <256 x double> @llvm.ve.vl.veqv.vvvvl(<256 x double> %0, <256 x double> %1, <256 x double> %2, i32 128)
+ ret <256 x double> %4
+}
+
+; Function Attrs: nounwind readnone
+declare <256 x double> @llvm.ve.vl.veqv.vvvvl(<256 x double>, <256 x double>, <256 x double>, i32)
+
+; Function Attrs: nounwind readnone
+define fastcc <256 x double> @veqv_vsvl(i64 %0, <256 x double> %1) {
+; CHECK-LABEL: veqv_vsvl:
+; CHECK: # %bb.0:
+; CHECK-NEXT: lea %s1, 256
+; CHECK-NEXT: lvl %s1
+; CHECK-NEXT: veqv %v0, %s0, %v0
+; CHECK-NEXT: b.l.t (, %s10)
+ %3 = tail call fast <256 x double> @llvm.ve.vl.veqv.vsvl(i64 %0, <256 x double> %1, i32 256)
+ ret <256 x double> %3
+}
+
+; Function Attrs: nounwind readnone
+declare <256 x double> @llvm.ve.vl.veqv.vsvl(i64, <256 x double>, i32)
+
+; Function Attrs: nounwind readnone
+define fastcc <256 x double> @veqv_vsvvl(i64 %0, <256 x double> %1, <256 x double> %2) {
+; CHECK-LABEL: veqv_vsvvl:
+; CHECK: # %bb.0:
+; CHECK-NEXT: lea %s1, 128
+; CHECK-NEXT: lvl %s1
+; CHECK-NEXT: veqv %v1, %s0, %v0
+; CHECK-NEXT: lea %s16, 256
+; CHECK-NEXT: lvl %s16
+; CHECK-NEXT: vor %v0, (0)1, %v1
+; CHECK-NEXT: b.l.t (, %s10)
+ %4 = tail call fast <256 x double> @llvm.ve.vl.veqv.vsvvl(i64 %0, <256 x double> %1, <256 x double> %2, i32 128)
+ ret <256 x double> %4
+}
+
+; Function Attrs: nounwind readnone
+declare <256 x double> @llvm.ve.vl.veqv.vsvvl(i64, <256 x double>, <256 x double>, i32)
+
+; Function Attrs: nounwind readnone
+define fastcc <256 x double> @veqv_vvvmvl(<256 x double> %0, <256 x double> %1, <256 x i1> %2, <256 x double> %3) {
+; CHECK-LABEL: veqv_vvvmvl:
+; CHECK: # %bb.0:
+; CHECK-NEXT: lea %s0, 128
+; CHECK-NEXT: lvl %s0
+; CHECK-NEXT: veqv %v2, %v0, %v1, %vm1
+; CHECK-NEXT: lea %s16, 256
+; CHECK-NEXT: lvl %s16
+; CHECK-NEXT: vor %v0, (0)1, %v2
+; CHECK-NEXT: b.l.t (, %s10)
+ %5 = tail call fast <256 x double> @llvm.ve.vl.veqv.vvvmvl(<256 x double> %0, <256 x double> %1, <256 x i1> %2, <256 x double> %3, i32 128)
+ ret <256 x double> %5
+}
+
+; Function Attrs: nounwind readnone
+declare <256 x double> @llvm.ve.vl.veqv.vvvmvl(<256 x double>, <256 x double>, <256 x i1>, <256 x double>, i32)
+
+; Function Attrs: nounwind readnone
+define fastcc <256 x double> @veqv_vsvmvl(i64 %0, <256 x double> %1, <256 x i1> %2, <256 x double> %3) {
+; CHECK-LABEL: veqv_vsvmvl:
+; CHECK: # %bb.0:
+; CHECK-NEXT: lea %s1, 128
+; CHECK-NEXT: lvl %s1
+; CHECK-NEXT: veqv %v1, %s0, %v0, %vm1
+; CHECK-NEXT: lea %s16, 256
+; CHECK-NEXT: lvl %s16
+; CHECK-NEXT: vor %v0, (0)1, %v1
+; CHECK-NEXT: b.l.t (, %s10)
+ %5 = tail call fast <256 x double> @llvm.ve.vl.veqv.vsvmvl(i64 %0, <256 x double> %1, <256 x i1> %2, <256 x double> %3, i32 128)
+ ret <256 x double> %5
+}
+
+; Function Attrs: nounwind readnone
+declare <256 x double> @llvm.ve.vl.veqv.vsvmvl(i64, <256 x double>, <256 x i1>, <256 x double>, i32)
+
+; Function Attrs: nounwind readnone
+define fastcc <256 x double> @pveqv_vvvl(<256 x double> %0, <256 x double> %1) {
+; CHECK-LABEL: pveqv_vvvl:
+; CHECK: # %bb.0:
+; CHECK-NEXT: lea %s0, 256
+; CHECK-NEXT: lvl %s0
+; CHECK-NEXT: pveqv %v0, %v0, %v1
+; CHECK-NEXT: b.l.t (, %s10)
+ %3 = tail call fast <256 x double> @llvm.ve.vl.pveqv.vvvl(<256 x double> %0, <256 x double> %1, i32 256)
+ ret <256 x double> %3
+}
+
+; Function Attrs: nounwind readnone
+declare <256 x double> @llvm.ve.vl.pveqv.vvvl(<256 x double>, <256 x double>, i32)
+
+; Function Attrs: nounwind readnone
+define fastcc <256 x double> @pveqv_vvvvl(<256 x double> %0, <256 x double> %1, <256 x double> %2) {
+; CHECK-LABEL: pveqv_vvvvl:
+; CHECK: # %bb.0:
+; CHECK-NEXT: lea %s0, 128
+; CHECK-NEXT: lvl %s0
+; CHECK-NEXT: pveqv %v2, %v0, %v1
+; CHECK-NEXT: lea %s16, 256
+; CHECK-NEXT: lvl %s16
+; CHECK-NEXT: vor %v0, (0)1, %v2
+; CHECK-NEXT: b.l.t (, %s10)
+ %4 = tail call fast <256 x double> @llvm.ve.vl.pveqv.vvvvl(<256 x double> %0, <256 x double> %1, <256 x double> %2, i32 128)
+ ret <256 x double> %4
+}
+
+; Function Attrs: nounwind readnone
+declare <256 x double> @llvm.ve.vl.pveqv.vvvvl(<256 x double>, <256 x double>, <256 x double>, i32)
+
+; Function Attrs: nounwind readnone
+define fastcc <256 x double> @pveqv_vsvl(i64 %0, <256 x double> %1) {
+; CHECK-LABEL: pveqv_vsvl:
+; CHECK: # %bb.0:
+; CHECK-NEXT: lea %s1, 256
+; CHECK-NEXT: lvl %s1
+; CHECK-NEXT: pveqv %v0, %s0, %v0
+; CHECK-NEXT: b.l.t (, %s10)
+ %3 = tail call fast <256 x double> @llvm.ve.vl.pveqv.vsvl(i64 %0, <256 x double> %1, i32 256)
+ ret <256 x double> %3
+}
+
+; Function Attrs: nounwind readnone
+declare <256 x double> @llvm.ve.vl.pveqv.vsvl(i64, <256 x double>, i32)
+
+; Function Attrs: nounwind readnone
+define fastcc <256 x double> @pveqv_vsvvl(i64 %0, <256 x double> %1, <256 x double> %2) {
+; CHECK-LABEL: pveqv_vsvvl:
+; CHECK: # %bb.0:
+; CHECK-NEXT: lea %s1, 128
+; CHECK-NEXT: lvl %s1
+; CHECK-NEXT: pveqv %v1, %s0, %v0
+; CHECK-NEXT: lea %s16, 256
+; CHECK-NEXT: lvl %s16
+; CHECK-NEXT: vor %v0, (0)1, %v1
+; CHECK-NEXT: b.l.t (, %s10)
+ %4 = tail call fast <256 x double> @llvm.ve.vl.pveqv.vsvvl(i64 %0, <256 x double> %1, <256 x double> %2, i32 128)
+ ret <256 x double> %4
+}
+
+; Function Attrs: nounwind readnone
+declare <256 x double> @llvm.ve.vl.pveqv.vsvvl(i64, <256 x double>, <256 x double>, i32)
+
+; Function Attrs: nounwind readnone
+define fastcc <256 x double> @pveqv_vvvMvl(<256 x double> %0, <256 x double> %1, <512 x i1> %2, <256 x double> %3) {
+; CHECK-LABEL: pveqv_vvvMvl:
+; CHECK: # %bb.0:
+; CHECK-NEXT: lea %s0, 128
+; CHECK-NEXT: lvl %s0
+; CHECK-NEXT: pveqv %v2, %v0, %v1, %vm2
+; CHECK-NEXT: lea %s16, 256
+; CHECK-NEXT: lvl %s16
+; CHECK-NEXT: vor %v0, (0)1, %v2
+; CHECK-NEXT: b.l.t (, %s10)
+ %5 = tail call fast <256 x double> @llvm.ve.vl.pveqv.vvvMvl(<256 x double> %0, <256 x double> %1, <512 x i1> %2, <256 x double> %3, i32 128)
+ ret <256 x double> %5
+}
+
+; Function Attrs: nounwind readnone
+declare <256 x double> @llvm.ve.vl.pveqv.vvvMvl(<256 x double>, <256 x double>, <512 x i1>, <256 x double>, i32)
+
+; Function Attrs: nounwind readnone
+define fastcc <256 x double> @pveqv_vsvMvl(i64 %0, <256 x double> %1, <512 x i1> %2, <256 x double> %3) {
+; CHECK-LABEL: pveqv_vsvMvl:
+; CHECK: # %bb.0:
+; CHECK-NEXT: lea %s1, 128
+; CHECK-NEXT: lvl %s1
+; CHECK-NEXT: pveqv %v1, %s0, %v0, %vm2
+; CHECK-NEXT: lea %s16, 256
+; CHECK-NEXT: lvl %s16
+; CHECK-NEXT: vor %v0, (0)1, %v1
+; CHECK-NEXT: b.l.t (, %s10)
+ %5 = tail call fast <256 x double> @llvm.ve.vl.pveqv.vsvMvl(i64 %0, <256 x double> %1, <512 x i1> %2, <256 x double> %3, i32 128)
+ ret <256 x double> %5
+}
+
+; Function Attrs: nounwind readnone
+declare <256 x double> @llvm.ve.vl.pveqv.vsvMvl(i64, <256 x double>, <512 x i1>, <256 x double>, i32)
diff --git a/llvm/test/CodeGen/VE/VELIntrinsics/vseq.ll b/llvm/test/CodeGen/VE/VELIntrinsics/vseq.ll
new file mode 100644
index 000000000000..78d69df7158b
--- /dev/null
+++ b/llvm/test/CodeGen/VE/VELIntrinsics/vseq.ll
@@ -0,0 +1,126 @@
+; RUN: llc < %s -mtriple=ve -mattr=+vpu | FileCheck %s
+
+;;; Test vector sequential number intrinsic instructions
+;;;
+;;; Note:
+;;; We test VSEQ*l, VSEQ*l_v, PVSEQ*l, and PVSEQ*l_v instructions.
+
+; Function Attrs: nounwind readnone
+define fastcc <256 x double> @vseq_vl() {
+; CHECK-LABEL: vseq_vl:
+; CHECK: # %bb.0:
+; CHECK-NEXT: lea %s0, 256
+; CHECK-NEXT: lvl %s0
+; CHECK-NEXT: vseq %v0
+; CHECK-NEXT: b.l.t (, %s10)
+ %1 = tail call fast <256 x double> @llvm.ve.vl.vseq.vl(i32 256)
+ ret <256 x double> %1
+}
+
+; Function Attrs: nounwind readnone
+declare <256 x double> @llvm.ve.vl.vseq.vl(i32)
+
+; Function Attrs: nounwind readnone
+define fastcc <256 x double> @vseq_vvl(<256 x double> %0) {
+; CHECK-LABEL: vseq_vvl:
+; CHECK: # %bb.0:
+; CHECK-NEXT: lea %s0, 256
+; CHECK-NEXT: lvl %s0
+; CHECK-NEXT: vseq %v0
+; CHECK-NEXT: b.l.t (, %s10)
+ %2 = tail call fast <256 x double> @llvm.ve.vl.vseq.vvl(<256 x double> %0, i32 256)
+ ret <256 x double> %2
+}
+
+; Function Attrs: nounwind readnone
+declare <256 x double> @llvm.ve.vl.vseq.vvl(<256 x double>, i32)
+
+; Function Attrs: nounwind readnone
+define fastcc <256 x double> @pvseqlo_vl() {
+; CHECK-LABEL: pvseqlo_vl:
+; CHECK: # %bb.0:
+; CHECK-NEXT: lea %s0, 256
+; CHECK-NEXT: lvl %s0
+; CHECK-NEXT: pvseq.lo %v0
+; CHECK-NEXT: b.l.t (, %s10)
+ %1 = tail call fast <256 x double> @llvm.ve.vl.pvseqlo.vl(i32 256)
+ ret <256 x double> %1
+}
+
+; Function Attrs: nounwind readnone
+declare <256 x double> @llvm.ve.vl.pvseqlo.vl(i32)
+
+; Function Attrs: nounwind readnone
+define fastcc <256 x double> @pvseqlo_vvl(<256 x double> %0) {
+; CHECK-LABEL: pvseqlo_vvl:
+; CHECK: # %bb.0:
+; CHECK-NEXT: lea %s0, 256
+; CHECK-NEXT: lvl %s0
+; CHECK-NEXT: pvseq.lo %v0
+; CHECK-NEXT: b.l.t (, %s10)
+ %2 = tail call fast <256 x double> @llvm.ve.vl.pvseqlo.vvl(<256 x double> %0, i32 256)
+ ret <256 x double> %2
+}
+
+; Function Attrs: nounwind readnone
+declare <256 x double> @llvm.ve.vl.pvseqlo.vvl(<256 x double>, i32)
+
+; Function Attrs: nounwind readnone
+define fastcc <256 x double> @pvsequp_vl() {
+; CHECK-LABEL: pvsequp_vl:
+; CHECK: # %bb.0:
+; CHECK-NEXT: lea %s0, 256
+; CHECK-NEXT: lvl %s0
+; CHECK-NEXT: pvseq.up %v0
+; CHECK-NEXT: b.l.t (, %s10)
+ %1 = tail call fast <256 x double> @llvm.ve.vl.pvsequp.vl(i32 256)
+ ret <256 x double> %1
+}
+
+; Function Attrs: nounwind readnone
+declare <256 x double> @llvm.ve.vl.pvsequp.vl(i32)
+
+; Function Attrs: nounwind readnone
+define fastcc <256 x double> @pvsequp_vvl(<256 x double> %0) {
+; CHECK-LABEL: pvsequp_vvl:
+; CHECK: # %bb.0:
+; CHECK-NEXT: lea %s0, 256
+; CHECK-NEXT: lvl %s0
+; CHECK-NEXT: pvseq.up %v0
+; CHECK-NEXT: b.l.t (, %s10)
+ %2 = tail call fast <256 x double> @llvm.ve.vl.pvsequp.vvl(<256 x double> %0, i32 256)
+ ret <256 x double> %2
+}
+
+; Function Attrs: nounwind readnone
+declare <256 x double> @llvm.ve.vl.pvsequp.vvl(<256 x double>, i32)
+
+; Function Attrs: nounwind readnone
+define fastcc <256 x double> @pvseq_vl() {
+; CHECK-LABEL: pvseq_vl:
+; CHECK: # %bb.0:
+; CHECK-NEXT: lea %s0, 256
+; CHECK-NEXT: lvl %s0
+; CHECK-NEXT: pvseq %v0
+; CHECK-NEXT: b.l.t (, %s10)
+ %1 = tail call fast <256 x double> @llvm.ve.vl.pvseq.vl(i32 256)
+ ret <256 x double> %1
+}
+
+; Function Attrs: nounwind readnone
+declare <256 x double> @llvm.ve.vl.pvseq.vl(i32)
+
+; Function Attrs: nounwind readnone
+define fastcc <256 x double> @pvseq_vvl(<256 x double> %0) {
+; CHECK-LABEL: pvseq_vvl:
+; CHECK: # %bb.0:
+; CHECK-NEXT: lea %s0, 256
+; CHECK-NEXT: lvl %s0
+; CHECK-NEXT: pvseq %v0
+; CHECK-NEXT: b.l.t (, %s10)
+ %2 = tail call fast <256 x double> @llvm.ve.vl.pvseq.vvl(<256 x double> %0, i32 256)
+ ret <256 x double> %2
+}
+
+; Function Attrs: nounwind readnone
+declare <256 x double> @llvm.ve.vl.pvseq.vvl(<256 x double>, i32)
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