[PATCH] D72184: [BPF] support atomic instructions

[Yonghong Song via Phabricator via llvm-commits]

yonghong-song added inline comments.


================
Comment at: llvm/lib/Target/BPF/BPFMIChecking.cpp:199
+      unsigned newOpcode;
+      switch(MI.getOpcode()) {
+      case BPF::XFADDW32: newOpcode = BPF::XADDW32; break;
----------------
yonghong-song wrote:
> ast wrote:
> > With this logic in place Andrii has a point. There is no need for -mcpu=v4 flag.
> > The builtins will produce new insns and it will be up to kernel to accept them or not.
> will make the change (removing -mcpu=v4).
There will be one user-level change:
  . if user has "ret = __sync_fetch_and_add(p, r);", today's llvm will generate a fatal error saying that invalid XADD since return value is used.
  . but removing -mcpu=v4. the compilation will be successful and the error will happen in kernel since atomic_fetch_add is not supported.

I guess this is an okay change, right?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D72184/new/

https://reviews.llvm.org/D72184