[PATCH] D90738: [RISCV] Support Zfh half-precision floating-point extension.

[Jessica Clarke via Phabricator via llvm-commits]

jrtc27 added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.h:53-59
+  // FPR32/FPR16<->GPR transfer operations for RV64/RV32. Needed as an i32<->f32
+  // and i16<->f16 bitcast are not legal on RV64/RV32. FMV_W_X_RV64 matches the
+  // semantics of the FMV.W.X. FMV_X_ANYEXTW_RV64 is similar to FMV.X.W but has
+  // an any-extended result. FMV_H_X_RV32/RV64 match the semantics of the
+  // FMV.H.X. FMV_X_ANYEXTH_RV32/RV64  are similar to FMV.X.H but has an
+  // any-extended result. This is a more convenient semantic for producing
+  // dagcombines that remove unnecessary GPR->FPR->GPR moves.
----------------
jrtc27 wrote:
> Comment should be updated to reflect the sorted order. It's also unclear which combinations are invalid; currently it could be interpreted as f16 only being an issue on RV32.
Still not clear that:
(a) i16<->f16 is a problem everywhere
(b) i32<->f32 is a problem only for RV64

Maybe it's best to generalise the opening paragraph to something like:
> FPR<->GPR transfer operations when the FPR is smaller than XLEN, needed as XLEN is the only legal integer width.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D90738/new/

https://reviews.llvm.org/D90738