[PATCH] D89449: [RISCV] Initial infrastructure for code generation of the RISC-V V-extension
Craig Topper via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Tue Dec 1 11:44:18 PST 2020
craig.topper updated this revision to Diff 308722.
craig.topper added a comment.
-Simplify the code in RISCVExpandPseudoInsts by using MBBI directly instead of creating MI from it and using the TII pointer already in the class.
-Copy the dead flag from the dest register when expanding PseudoVSETVLI.
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D89449/new/
https://reviews.llvm.org/D89449
Files:
llvm/lib/Target/RISCV/RISCV.h
llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp
llvm/lib/Target/RISCV/RISCVISelLowering.cpp
llvm/lib/Target/RISCV/RISCVInstrInfoPseudoV.td
llvm/lib/Target/RISCV/RISCVInstrInfoV.td
llvm/lib/Target/RISCV/RISCVMCInstLower.cpp
llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
llvm/lib/Target/RISCV/RISCVRegisterInfo.td
llvm/lib/Target/RISCV/Utils/RISCVBaseInfo.cpp
llvm/lib/Target/RISCV/Utils/RISCVBaseInfo.h
llvm/test/CodeGen/RISCV/rvv/add-vsetvli-gpr.mir
llvm/test/CodeGen/RISCV/rvv/add-vsetvli-vlmax.ll
llvm/test/CodeGen/RISCV/rvv/load-add-store-16.ll
llvm/test/CodeGen/RISCV/rvv/load-add-store-32.ll
llvm/test/CodeGen/RISCV/rvv/load-add-store-64.ll
llvm/test/CodeGen/RISCV/rvv/load-add-store-8.ll
llvm/utils/TableGen/GlobalISelEmitter.cpp
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