[PATCH] D92213: [ARM] PREDICATE_CAST demanded bits

[Dave Green via Phabricator via llvm-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rG7923d71b4a7a: [ARM] PREDICATE_CAST demanded bits (authored by dmgreen).

Changed prior to commit:
  https://reviews.llvm.org/D92213?vs=307982&id=308598#toc

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D92213/new/

https://reviews.llvm.org/D92213

Files:
  llvm/lib/Target/ARM/ARMISelLowering.cpp
  llvm/test/CodeGen/Thumb2/mve-pred-bitcast.ll
  llvm/test/CodeGen/Thumb2/mve-pred-constfold.ll


Index: llvm/test/CodeGen/Thumb2/mve-pred-constfold.ll
===================================================================
--- llvm/test/CodeGen/Thumb2/mve-pred-constfold.ll
+++ llvm/test/CodeGen/Thumb2/mve-pred-constfold.ll
@@ -51,10 +51,8 @@
 ; CHECK:       @ %bb.0: @ %entry
 ; CHECK-NEXT:    .save {r4, r6, r7, lr}
 ; CHECK-NEXT:    push {r4, r6, r7, lr}
-; CHECK-NEXT:    uxth r2, r1
+; CHECK-NEXT:    vmsr p0, r1
 ; CHECK-NEXT:    mvns r1, r1
-; CHECK-NEXT:    vmsr p0, r2
-; CHECK-NEXT:    uxth r1, r1
 ; CHECK-NEXT:    vpstt
 ; CHECK-NEXT:    vaddvt.s16 r12, q1
 ; CHECK-NEXT:    vaddvt.s16 r2, q0
@@ -92,7 +90,6 @@
 ; CHECK:       @ %bb.0: @ %entry
 ; CHECK-NEXT:    mvns r0, r0
 ; CHECK-NEXT:    vmov.i32 q1, #0x0
-; CHECK-NEXT:    uxth r0, r0
 ; CHECK-NEXT:    vmsr p0, r0
 ; CHECK-NEXT:    vpsel q0, q0, q1
 ; CHECK-NEXT:    bx lr
@@ -109,7 +106,6 @@
 ; CHECK:       @ %bb.0: @ %entry
 ; CHECK-NEXT:    mvns r0, r0
 ; CHECK-NEXT:    vmov.i32 q1, #0x0
-; CHECK-NEXT:    uxth r0, r0
 ; CHECK-NEXT:    vmsr p0, r0
 ; CHECK-NEXT:    vpsel q0, q0, q1
 ; CHECK-NEXT:    bx lr
@@ -126,7 +122,6 @@
 ; CHECK:       @ %bb.0: @ %entry
 ; CHECK-NEXT:    mvns r0, r0
 ; CHECK-NEXT:    vmov.i32 q1, #0x0
-; CHECK-NEXT:    uxth r0, r0
 ; CHECK-NEXT:    vmsr p0, r0
 ; CHECK-NEXT:    vpsel q0, q0, q1
 ; CHECK-NEXT:    bx lr
Index: llvm/test/CodeGen/Thumb2/mve-pred-bitcast.ll
===================================================================
--- llvm/test/CodeGen/Thumb2/mve-pred-bitcast.ll
+++ llvm/test/CodeGen/Thumb2/mve-pred-bitcast.ll
@@ -139,10 +139,9 @@
 ; CHECK-LE-NEXT:    mov r4, sp
 ; CHECK-LE-NEXT:    bfc r4, #0, #4
 ; CHECK-LE-NEXT:    mov sp, r4
-; CHECK-LE-NEXT:    uxth r0, r0
 ; CHECK-LE-NEXT:    sub.w r4, r7, #8
-; CHECK-LE-NEXT:    vmov.i32 q1, #0x0
 ; CHECK-LE-NEXT:    vmsr p0, r0
+; CHECK-LE-NEXT:    vmov.i32 q1, #0x0
 ; CHECK-LE-NEXT:    vpsel q0, q0, q1
 ; CHECK-LE-NEXT:    mov sp, r4
 ; CHECK-LE-NEXT:    pop {r4, r6, r7, pc}
@@ -160,7 +159,6 @@
 ; CHECK-BE-NEXT:    mov sp, r4
 ; CHECK-BE-NEXT:    vrev64.8 q1, q0
 ; CHECK-BE-NEXT:    vmov.i32 q0, #0x0
-; CHECK-BE-NEXT:    uxth r0, r0
 ; CHECK-BE-NEXT:    sub.w r4, r7, #8
 ; CHECK-BE-NEXT:    vrev32.8 q0, q0
 ; CHECK-BE-NEXT:    vmsr p0, r0
Index: llvm/lib/Target/ARM/ARMISelLowering.cpp
===================================================================
--- llvm/lib/Target/ARM/ARMISelLowering.cpp
+++ llvm/lib/Target/ARM/ARMISelLowering.cpp
@@ -13844,6 +13844,13 @@
     return DCI.DAG.getNode(ARMISD::PREDICATE_CAST, dl, VT, Op->getOperand(0));
   }
 
+  // Only the bottom 16 bits of the source register are used.
+  if (Op.getValueType() == MVT::i32) {
+    APInt DemandedMask = APInt::getLowBitsSet(32, 16);
+    const TargetLowering &TLI = DCI.DAG.getTargetLoweringInfo();
+    if (TLI.SimplifyDemandedBits(Op, DemandedMask, DCI))
+      return SDValue(N, 0);
+  }
   return SDValue();
 }
 


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