[PATCH] D92324: [PowerPC] Fix altivec feature on pwr cpus pre pwr6.

[Sean Fertile via Phabricator via llvm-commits]

sfertile added a comment.

In D92324#2422992 <https://reviews.llvm.org/D92324#2422992>, @hubert.reinterpretcast wrote:

>> The altivec feature was an optional part of the 2.03 (pwr4) and 2.04 (pwr5) ISAs, and it was not implemented by any IBM CPUs until Power6.
>
> The Power Processing Element in various IBM CPUs (including the Cell Broadband Engine) incorporate VMX. With this change, which of the CPU options should a user targeting a PPE use?

I'm not really familiar with PPEs or CELL, but my understanding was that the generic `ppc64` was what they targeted. From your question I'm guessing that understanding is wrong. If the best CPU to target for a PPE is one of the ones modified in this patch, they can still do so, but will have to explicitly add `-mattr=+altivec` when invoking llc. IR with '-mattr=+altivec,...` will continue to enable altivec as well. If there are no objections I'll add `-mattr=+altivec' to the vector-popcnt-128-ult-ugt.ll test, and add a test showing that the altivec attribute continues to work on pwr4/5.


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https://reviews.llvm.org/D92324