[PATCH] D92230: [SVE][CodeGen] Add DAG combines for s/zext_masked_gather

[Sander de Smalen via Phabricator via llvm-commits]

sdesmalen added inline comments.


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Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:3888
       Index.getSimpleValueType().getVectorElementType() == MVT::i32;
+  bool ResNeedsExtend = ExtTy == ISD::EXTLOAD || ExtTy == ISD::SEXTLOAD;
 
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nit: s/ResNeedsExtend/ResNeedsSignExtend/ ?


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Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:3917
+  if (ResNeedsExtend)
+    Opcode = getExtendedGatherOpcode(Opcode);
+
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nit: `s/getExtendedGatherOpcode/getSignExtendedGatherOpcode/`


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Comment at: llvm/test/CodeGen/AArch64/sve-masked-gather-legalize.ll:7
+
+define <vscale x 2 x i64> @masked_sgather_nxv2i8(i8* %base, <vscale x 2 x i64> %offsets, <vscale x 2 x i1> %mask, <vscale x 2 x i8> %vals) {
+; CHECK-LABEL: masked_sgather_nxv2i8:
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Can you add a similar test with zero-extend?


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  https://reviews.llvm.org/D92230/new/

https://reviews.llvm.org/D92230