[PATCH] D88044: [llvm-exegesis][PowerPC] Add more register classes

[Qiu Chaofan via Phabricator via llvm-commits]

qiucf added a comment.

Thanks for the patch! I think code added is quite clear since most of them already exist as framework in implementation of other platforms. We can continue to support more about exegesis on PowerPC in later patches.

Besides, I found `llvm-exegesis -mode=latency -opcode-name=XSTDIVDP` complains 'illegal instruction' on ppc64le-pwr9, which looks strange. Is that because we did not model CR well in this tool?



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Comment at: llvm/lib/Target/PowerPC/PPCInstr64Bit.td:22
   let DecoderMethod = "decodeSImmOperand<16>";
+  let OperandType = "OPERAND_IMMEDIATE";
 }
----------------
So, we will mark `OPERAND_REGISTER` in future patches?


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Comment at: llvm/tools/llvm-exegesis/lib/PowerPC/Target.cpp:111
+            MCInstBuilder(PPC::MTVRD).addReg(Reg).addReg(ScratchImmReg)};
+  if (PPC::VSRCRegClass.contains(Reg))
+    return {loadImmediate(ScratchImmReg, 64, Value),
----------------
I applied this patch and tested `XSDIVDP`, still got 2 lines of warning `setRegTo is not implemented, results will be unreliable` (before this patch, that is six). Is that from `RM` and can be ignored?


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https://reviews.llvm.org/D88044