[PATCH] D91048: [AMDGPU] Add new pseudos for indirect addressing with VGPR Indexing

[Matt Arsenault via Phabricator via llvm-commits]

arsenm added inline comments.


================
Comment at: llvm/test/CodeGen/AMDGPU/expand-si-indirect.mir:25
+
+    %1:sgpr_64(p4) = COPY killed $sgpr0_sgpr1
+    %4:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
----------------
Can strip out the type, it's a minor bug this exists here


================
Comment at: llvm/test/CodeGen/AMDGPU/expand-si-indirect.mir:35
+    %84:vgpr_32 = V_MOV_B32_e32 1084227584, implicit $exec
+    %85:vgpr_32 = V_MOV_B32_e32 1086324736, implicit $exec
+    %86:vgpr_32 = V_MOV_B32_e32 1088421888, implicit $exec
----------------
Can you -run-pass=none to compact the register numbers


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D91048/new/

https://reviews.llvm.org/D91048