[PATCH] D92096: [SelectionDAGBuilder] Update signature of `getRegsAndSizes()`.

[Matt Arsenault via Phabricator via llvm-commits]

arsenm accepted this revision.
arsenm added inline comments.
This revision is now accepted and ready to land.


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Comment at: llvm/test/CodeGen/AArch64/sdag-no-typesize-warnings-regandsizes.ll:24
+!llvm.module.flags = !{!3, !4}
+!llvm.ident = !{!5}
+
----------------
This is removable


================
Comment at: llvm/test/CodeGen/AArch64/sdag-no-typesize-warnings-regandsizes.ll:33
+!6 = !DILocalVariable(name: "vx", arg: 1, scope: !7, file: !1, line: 3, type: !10)
+!7 = distinct !DISubprogram(name: "do_something", scope: !1, file: !1, line: 3, type: !8, scopeLine: 3, flags: DIFlagPrototyped | DIFlagAllCallsDescribed, spFlags: DISPFlagDefinition | DISPFlagOptimized, unit: !0, retainedNodes: !17)
+!8 = !DISubroutineType(types: !9)
----------------
It is possible to hack on the fields here but it's a pain


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D92096/new/

https://reviews.llvm.org/D92096