[PATCH] D91487: [AMDGPU] Don't require swz operand for non-return Atomics.

[Matthew Dawson via Phabricator via llvm-commits]

MJDSys added a comment.

In D91487#2397822 <https://reviews.llvm.org/D91487#2397822>, @rampitec wrote:

> Needs test.

Hi @rampitec,

I've tried writing a test for this change, but I've been having trouble (I'm new to LLVM so I might be missing the obvious answer).  From what I can see, I thought the correct option would be to create a MIR test, using the same instruction that I saw when investigating the original problem.  I started by copying and modifying an existing test in fix-sgpr-copies.mir:

  # Test to ensure non-return buffer atomics work
  # GCN-LABEL: name: non-return-buffer-atomic
  # GCN: S_CSELECT_B64 -1, 0, implicit undef $scc
  # GCN: V_CNDMASK
  ---
  name: non-return-buffer-atomic
  tracksRegLiveness: true
  
  body:               |
    bb.0:
    %1:vreg_64 = IMPLICIT_DEF
    %2:vreg_128 = IMPLICIT_DEF
    BUFFER_ATOMIC_OR_X2_OFFSET %1, %2, 0, 0, 0, implicit $exec
  ---

However, when I try running the test I get an assert happening, with LLVM complaining the machine code is incorrect due to an illegal virtual register.  I got stuck here as I'm trying to create an instruction with an incorrect register to have the code fix it (same as what is done in the failing pass).  I'm not sure how to proceed, do you have any suggestion/pointers?  Or an alternate test I can use as a template?  Note: I'm aware the expected output of the test was incorrect, I was first wanting to verify the test output manually before making it work during a normal test run.

Thanks,

Matthew


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https://reviews.llvm.org/D91487