[PATCH] D92286: [RISCV] Form GORCI from (or (rotl/rotr X, Bitwidth/2), X).

Craig Topper via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Sun Nov 29 13:49:23 PST 2020

craig.topper created this revision.
craig.topper added reviewers: frasercrmck, asb, lenary, luismarques.
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A rotate by half the bitwidth swaps the bottom and top half which is the same as one of the MSB GREVI stage.

  rG LLVM Github Monorepo



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