[PATCH] D71124: [RISCV] support clang driver to select cpu
Ivan Serdyuk via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Thu Nov 26 07:39:44 PST 2020
oceanfish81 added a comment.
@khchen , what is the recomended way to get the current CPU features?
I see that there are some ISA extensions defined here <https://code.woboq.org/llvm/clang/lib/Driver/ToolChains/Arch/RISCV.cpp.html> .
So RISC-V back-end has another API, for both identifying available CPU (or vCPU, if under Qemu) features?
How does the CLI options correspond with the back-end capabilities?
There is some code, for gollvm project https://go.googlesource.com/gollvm/+/e3ede8ef8009429eaae91bbae2d67542ddaa5853/tools/capture-fcn-attributes.go - and it relies on https://github.com/llvm/llvm-project/blob/48ddf5e182c61cb93d66325f5690312d9e9226eb/llvm/lib/Support/Host.cpp (auto-generation).
I need to understand whethershould Host.cpp be patched or should I use an arch. specific/dedicated workaround.
I am forcasting sgnificant contrast in gollvm's adoption, between various RISC-V boards, since of an active usage of different CPU features (available on one micro-controller, with others unavailable - and vice versa).
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