[PATCH] D91416: [VE] LVLGen sets VL before vector insts

[Kazushi Marukawa via Phabricator via llvm-commits]

kaz7 added inline comments.


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Comment at: llvm/lib/Target/VE/LVLGen.cpp:92
+      // Old VL is overwritten, so disable HasRegForVL.
+      if (MI->findRegisterDefOperandIdx(RegForVL, false, false, TRI) != -1) {
+        LLVM_DEBUG(dbgs() << RegName(RegForVL) << " is killed: ");
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craig.topper wrote:
> Does this handle the case of a call in the middle of a group of vector instructions? Such a call might modify VL. But I don't think the call will show VL as a def for findRegisterDefOperandIdx.
No, this doesn't handle such case and generates wrong instructions.  Thank you for suggestions.  I'll prepare updates.


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  https://reviews.llvm.org/D91416/new/

https://reviews.llvm.org/D91416