[PATCH] D92128: [RISCV][LegalizeTypes] Teach type legalizer that it can promote UMIN/UMAX using SExtPromotedInteger if that's better for the target.
Craig Topper via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Fri Nov 27 11:39:27 PST 2020
This revision was automatically updated to reflect the committed changes.
Closed by commit rGfa0f01a3c0e1: [RISCV][LegalizeTypes] Teach type legalizer that it can promote UMIN/UMAX using… (authored by craig.topper).
Herald added a subscriber: jrtc27.
Changed prior to commit:
https://reviews.llvm.org/D92128?vs=307698&id=308096#toc
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D92128/new/
https://reviews.llvm.org/D92128
Files:
llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
llvm/test/CodeGen/RISCV/rv64Zbb.ll
Index: llvm/test/CodeGen/RISCV/rv64Zbb.ll
===================================================================
--- llvm/test/CodeGen/RISCV/rv64Zbb.ll
+++ llvm/test/CodeGen/RISCV/rv64Zbb.ll
@@ -856,18 +856,12 @@
;
; RV64IB-LABEL: minu_i32:
; RV64IB: # %bb.0:
-; RV64IB-NEXT: zext.w a1, a1
-; RV64IB-NEXT: zext.w a0, a0
; RV64IB-NEXT: minu a0, a0, a1
-; RV64IB-NEXT: sext.w a0, a0
; RV64IB-NEXT: ret
;
; RV64IBB-LABEL: minu_i32:
; RV64IBB: # %bb.0:
-; RV64IBB-NEXT: zext.w a1, a1
-; RV64IBB-NEXT: zext.w a0, a0
; RV64IBB-NEXT: minu a0, a0, a1
-; RV64IBB-NEXT: sext.w a0, a0
; RV64IBB-NEXT: ret
%cmp = icmp ult i32 %a, %b
%cond = select i1 %cmp, i32 %a, i32 %b
@@ -908,18 +902,12 @@
;
; RV64IB-LABEL: maxu_i32:
; RV64IB: # %bb.0:
-; RV64IB-NEXT: zext.w a1, a1
-; RV64IB-NEXT: zext.w a0, a0
; RV64IB-NEXT: maxu a0, a0, a1
-; RV64IB-NEXT: sext.w a0, a0
; RV64IB-NEXT: ret
;
; RV64IBB-LABEL: maxu_i32:
; RV64IBB: # %bb.0:
-; RV64IBB-NEXT: zext.w a1, a1
-; RV64IBB-NEXT: zext.w a0, a0
; RV64IBB-NEXT: maxu a0, a0, a1
-; RV64IBB-NEXT: sext.w a0, a0
; RV64IBB-NEXT: ret
%cmp = icmp ugt i32 %a, %b
%cond = select i1 %cmp, i32 %a, i32 %b
Index: llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
===================================================================
--- llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
+++ llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
@@ -331,6 +331,7 @@
SDValue PromoteIntRes_SimpleIntBinOp(SDNode *N);
SDValue PromoteIntRes_ZExtIntBinOp(SDNode *N);
SDValue PromoteIntRes_SExtIntBinOp(SDNode *N);
+ SDValue PromoteIntRes_UMINUMAX(SDNode *N);
SDValue PromoteIntRes_SIGN_EXTEND_INREG(SDNode *N);
SDValue PromoteIntRes_SRA(SDNode *N);
SDValue PromoteIntRes_SRL(SDNode *N);
Index: llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
===================================================================
--- llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
+++ llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
@@ -82,7 +82,7 @@
case ISD::SMIN:
case ISD::SMAX: Res = PromoteIntRes_SExtIntBinOp(N); break;
case ISD::UMIN:
- case ISD::UMAX: Res = PromoteIntRes_ZExtIntBinOp(N); break;
+ case ISD::UMAX: Res = PromoteIntRes_UMINUMAX(N); break;
case ISD::SHL: Res = PromoteIntRes_SHL(N); break;
case ISD::SIGN_EXTEND_INREG:
@@ -1101,6 +1101,15 @@
LHS.getValueType(), LHS, RHS);
}
+SDValue DAGTypeLegalizer::PromoteIntRes_UMINUMAX(SDNode *N) {
+ // It doesn't matter if we sign extend or zero extend in the inputs. So do
+ // whatever is best for the target.
+ SDValue LHS = SExtOrZExtPromotedInteger(N->getOperand(0));
+ SDValue RHS = SExtOrZExtPromotedInteger(N->getOperand(1));
+ return DAG.getNode(N->getOpcode(), SDLoc(N),
+ LHS.getValueType(), LHS, RHS);
+}
+
SDValue DAGTypeLegalizer::PromoteIntRes_SRA(SDNode *N) {
// The input value must be properly sign extended.
SDValue LHS = SExtPromotedInteger(N->getOperand(0));
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