[PATCH] D90479: [ValueTracking] ComputeKnownBits - minimum leading/trailing zero bits in LSHR/SHL (PR44526)

[Simon Pilgrim via Phabricator via llvm-commits]

RKSimon updated this revision to Diff 308079.
RKSimon retitled this revision from "[WIP][ValueTracking] ComputeKnownBits - minimum leading/trailing zero bits in LSHR/SHL (PR44526)" to "[ValueTracking] ComputeKnownBits - minimum leading/trailing zero bits in LSHR/SHL (PR44526)".
RKSimon edited the summary of this revision.
RKSimon added a comment.

Move the and(logical_shift(1, X), 1) --> zext(X == 0) earlier so SimplifyDemandedInstructionBits doesn't remove the pattern.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D90479/new/

https://reviews.llvm.org/D90479

Files:
  llvm/lib/Analysis/ValueTracking.cpp
  llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp
  llvm/test/Transforms/InstCombine/and2.ll
  llvm/test/Transforms/InstCombine/lshr-and-negC-icmpeq-zero.ll
  llvm/test/Transforms/InstCombine/signbit-shl-and-icmpeq-zero.ll
  llvm/test/Transforms/InstCombine/zext-or-icmp.ll

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