[PATCH] D92235: [ARM] Turn pred_cast(xor(x, -1)) into xor(pred_cast(x), -1)

[Dave Green via Phabricator via llvm-commits]

dmgreen created this revision.
dmgreen added reviewers: samtebbs, simon_tatham, SjoerdMeijer, efriedma, ostannard.
Herald added subscribers: danielkiss, hiraditya, kristof.beyls.
Herald added a project: LLVM.
dmgreen requested review of this revision.

This folds a `not` (an `xor -1`) though a `predicate_cast`, so that it can be turned into a `VPNOT` and potentially be folded away as an "else" predicate inside a VPT block.


https://reviews.llvm.org/D92235

Files:
  llvm/lib/Target/ARM/ARMISelLowering.cpp
  llvm/test/CodeGen/Thumb2/mve-pred-constfold.ll


Index: llvm/test/CodeGen/Thumb2/mve-pred-constfold.ll
===================================================================
--- llvm/test/CodeGen/Thumb2/mve-pred-constfold.ll
+++ llvm/test/CodeGen/Thumb2/mve-pred-constfold.ll
@@ -52,14 +52,11 @@
 ; CHECK-NEXT:    .save {r4, r6, r7, lr}
 ; CHECK-NEXT:    push {r4, r6, r7, lr}
 ; CHECK-NEXT:    vmsr p0, r1
-; CHECK-NEXT:    mvns r1, r1
-; CHECK-NEXT:    vpstt
+; CHECK-NEXT:    vpsttee
 ; CHECK-NEXT:    vaddvt.s16 r12, q1
 ; CHECK-NEXT:    vaddvt.s16 r2, q0
-; CHECK-NEXT:    vmsr p0, r1
-; CHECK-NEXT:    vpstt
-; CHECK-NEXT:    vaddvt.s16 r4, q1
-; CHECK-NEXT:    vaddvt.s16 r6, q0
+; CHECK-NEXT:    vaddve.s16 r4, q1
+; CHECK-NEXT:    vaddve.s16 r6, q0
 ; CHECK-NEXT:    stm.w r0, {r2, r6, r12}
 ; CHECK-NEXT:    str r4, [r0, #12]
 ; CHECK-NEXT:    pop {r4, r6, r7, pc}
@@ -88,9 +85,9 @@
 define arm_aapcs_vfpcc <4 x i32> @xorvpnot_i32(<4 x i32> %acc0, i16 signext %p0) {
 ; CHECK-LABEL: xorvpnot_i32:
 ; CHECK:       @ %bb.0: @ %entry
-; CHECK-NEXT:    mvns r0, r0
-; CHECK-NEXT:    vmov.i32 q1, #0x0
 ; CHECK-NEXT:    vmsr p0, r0
+; CHECK-NEXT:    vmov.i32 q1, #0x0
+; CHECK-NEXT:    vpnot
 ; CHECK-NEXT:    vpsel q0, q0, q1
 ; CHECK-NEXT:    bx lr
 entry:
@@ -104,9 +101,9 @@
 define arm_aapcs_vfpcc <8 x i16> @xorvpnot_i16(<8 x i16> %acc0, i16 signext %p0) {
 ; CHECK-LABEL: xorvpnot_i16:
 ; CHECK:       @ %bb.0: @ %entry
-; CHECK-NEXT:    mvns r0, r0
-; CHECK-NEXT:    vmov.i32 q1, #0x0
 ; CHECK-NEXT:    vmsr p0, r0
+; CHECK-NEXT:    vmov.i32 q1, #0x0
+; CHECK-NEXT:    vpnot
 ; CHECK-NEXT:    vpsel q0, q0, q1
 ; CHECK-NEXT:    bx lr
 entry:
@@ -120,9 +117,9 @@
 define arm_aapcs_vfpcc <16 x i8> @xorvpnot_i8(<16 x i8> %acc0, i16 signext %p0) {
 ; CHECK-LABEL: xorvpnot_i8:
 ; CHECK:       @ %bb.0: @ %entry
-; CHECK-NEXT:    mvns r0, r0
-; CHECK-NEXT:    vmov.i32 q1, #0x0
 ; CHECK-NEXT:    vmsr p0, r0
+; CHECK-NEXT:    vmov.i32 q1, #0x0
+; CHECK-NEXT:    vpnot
 ; CHECK-NEXT:    vpsel q0, q0, q1
 ; CHECK-NEXT:    bx lr
 entry:
Index: llvm/lib/Target/ARM/ARMISelLowering.cpp
===================================================================
--- llvm/lib/Target/ARM/ARMISelLowering.cpp
+++ llvm/lib/Target/ARM/ARMISelLowering.cpp
@@ -13906,6 +13906,18 @@
     return DCI.DAG.getNode(ARMISD::PREDICATE_CAST, dl, VT, Op->getOperand(0));
   }
 
+  // Turn pred_cast(xor x, -1) into xor(pred_cast x, -1), in order to produce
+  // more VPNOT which might get folded as else predicates.
+  if (Op.getValueType() == MVT::i32 && Op.getOpcode() == ISD::XOR &&
+      isa<ConstantSDNode>(Op.getOperand(1)) &&
+      Op.getConstantOperandAPInt(1).isMask(32)) {
+    SDValue X =
+        DCI.DAG.getNode(ARMISD::PREDICATE_CAST, dl, VT, Op->getOperand(0));
+    SDValue C = DCI.DAG.getNode(ARMISD::PREDICATE_CAST, dl, VT,
+                                DCI.DAG.getConstant(65535, dl, MVT::i32));
+    return DCI.DAG.getNode(ISD::XOR, dl, VT, X, C);
+  }
+
   // Only the bottom 16 bits of the source register are used.
   if (Op.getValueType() == MVT::i32) {
     APInt DemandedMask = APInt::getLowBitsSet(32, 16);


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