[PATCH] D91933: [X86] Do not allow FixupSetCC to relax constraints

[Harald van Dijk via Phabricator via llvm-commits]

hvdijk updated this revision to Diff 307929.
hvdijk added a comment.

Add a comment about skipping the optimization when constraining fails.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D91933/new/

https://reviews.llvm.org/D91933

Files:
  llvm/lib/Target/X86/X86FixupSetCC.cpp
  llvm/test/CodeGen/X86/pic.ll


Index: llvm/test/CodeGen/X86/pic.ll
===================================================================
--- llvm/test/CodeGen/X86/pic.ll
+++ llvm/test/CodeGen/X86/pic.ll
@@ -1,6 +1,6 @@
-; RUN: llc < %s -mcpu=generic -mtriple=i686-pc-linux-gnu -relocation-model=pic -asm-verbose=false -post-RA-scheduler=false | FileCheck %s -check-prefixes=CHECK,CHECK-I686
-; RUN: llc < %s -mcpu=generic -mtriple=x86_64-pc-linux-gnux32 -relocation-model=pic -asm-verbose=false -post-RA-scheduler=false | FileCheck %s -check-prefixes=CHECK,CHECK-X32
-; RUN: llc < %s -mcpu=generic -mtriple=x86_64-pc-linux-gnux32 -relocation-model=pic -asm-verbose=false -post-RA-scheduler=false -fast-isel | FileCheck %s -check-prefixes=CHECK,CHECK-X32
+; RUN: llc < %s -mcpu=generic -mtriple=i686-pc-linux-gnu -relocation-model=pic -asm-verbose=false -post-RA-scheduler=false -verify-machineinstrs | FileCheck %s -check-prefixes=CHECK,CHECK-I686
+; RUN: llc < %s -mcpu=generic -mtriple=x86_64-pc-linux-gnux32 -relocation-model=pic -asm-verbose=false -post-RA-scheduler=false -verify-machineinstrs | FileCheck %s -check-prefixes=CHECK,CHECK-X32
+; RUN: llc < %s -mcpu=generic -mtriple=x86_64-pc-linux-gnux32 -relocation-model=pic -asm-verbose=false -post-RA-scheduler=false -fast-isel -verify-machineinstrs | FileCheck %s -check-prefixes=CHECK,CHECK-X32
 
 @ptr = external global i32* 
 @dst = external global i32 
Index: llvm/lib/Target/X86/X86FixupSetCC.cpp
===================================================================
--- llvm/lib/Target/X86/X86FixupSetCC.cpp
+++ llvm/lib/Target/X86/X86FixupSetCC.cpp
@@ -97,28 +97,31 @@
       if (FlagsDefMI->readsRegister(X86::EFLAGS))
         continue;
 
-      ++NumSubstZexts;
-      Changed = true;
-
       // On 32-bit, we need to be careful to force an ABCD register.
       const TargetRegisterClass *RC = MF.getSubtarget<X86Subtarget>().is64Bit()
                                           ? &X86::GR32RegClass
                                           : &X86::GR32_ABCDRegClass;
-      Register ZeroReg = MRI->createVirtualRegister(RC);
-      Register InsertReg = MRI->createVirtualRegister(RC);
+      if (!MRI->constrainRegClass(ZExt->getOperand(0).getReg(), RC)) {
+        // If we cannot constrain the register, we would need an additional copy
+        // and are better off keeping the MOVZX32rr8 we have now.
+        continue;
+      }
+
+      ++NumSubstZexts;
+      Changed = true;
 
       // Initialize a register with 0. This must go before the eflags def
+      Register ZeroReg = MRI->createVirtualRegister(RC);
       BuildMI(MBB, FlagsDefMI, MI.getDebugLoc(), TII->get(X86::MOV32r0),
               ZeroReg);
 
       // X86 setcc only takes an output GR8, so fake a GR32 input by inserting
       // the setcc result into the low byte of the zeroed register.
       BuildMI(*ZExt->getParent(), ZExt, ZExt->getDebugLoc(),
-              TII->get(X86::INSERT_SUBREG), InsertReg)
+              TII->get(X86::INSERT_SUBREG), ZExt->getOperand(0).getReg())
           .addReg(ZeroReg)
           .addReg(MI.getOperand(0).getReg())
           .addImm(X86::sub_8bit);
-      MRI->replaceRegWith(ZExt->getOperand(0).getReg(), InsertReg);
       ToErase.push_back(ZExt);
     }
   }


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