[PATCH] D91589: [DAGCombiner] Fold (sext (not i1 x)) -> (add (zext i1 x), -1)

[Layton Kifer via Phabricator via llvm-commits]

laytonio updated this revision to Diff 307908.
laytonio added a comment.

Use isBitwiseNot
Avoid folding cases where (not i1 x) can already be folded

Switch to only matching sign extends from scalar i1s. This is what the X86 backend is currently doing. I don't believe this transform is always better for vector types as it requires materializing an all ones vector.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D91589/new/

https://reviews.llvm.org/D91589

Files:
  llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
  llvm/lib/Target/X86/X86ISelLowering.cpp
  llvm/test/CodeGen/AArch64/select_const.ll
  llvm/test/CodeGen/ARM/select_const.ll
  llvm/test/CodeGen/PowerPC/select_const.ll
  llvm/test/CodeGen/RISCV/sext-zext-trunc.ll
  llvm/test/CodeGen/SystemZ/sext-zext.ll
  llvm/test/CodeGen/X86/pr44140.ll

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