[PATCH] D76127: [TableGen] Do not set ReadOnly attribute on intrinsics with side effects

[Danila Malyutin via Phabricator via llvm-commits]

danilaml added a comment.

The diffs lack context.

It looks like there is some inconsistency between .td attributes/properties and IR ones.
As far as I can tell there is no way in IR to mark something as "this doesn't touch mem but may have other side-effects" so it'd be safe to, for example, move some load past that instruction but not to DCE/CSE it.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D76127/new/

https://reviews.llvm.org/D76127