[PATCH] D91363: [SVE][CodeGen] Extend isConstantSplatValue to support ISD::SPLAT_VECTOR
Kerry McLaughlin via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Thu Nov 26 03:24:39 PST 2020
This revision was automatically updated to reflect the committed changes.
kmclaughlin marked an inline comment as done.
Closed by commit rG4bee3197f665: [SVE][CodeGen] Extend isConstantSplatValue to support ISD::SPLAT_VECTOR (authored by kmclaughlin).
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D91363/new/
https://reviews.llvm.org/D91363
Files:
llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
llvm/test/CodeGen/AArch64/sve-gep.ll
Index: llvm/test/CodeGen/AArch64/sve-gep.ll
===================================================================
--- llvm/test/CodeGen/AArch64/sve-gep.ll
+++ llvm/test/CodeGen/AArch64/sve-gep.ll
@@ -105,11 +105,9 @@
; CHECK-LABEL: scalable_of_scalable_1:
; CHECK: // %bb.0:
; CHECK-NEXT: rdvl x8, #1
-; CHECK-NEXT: mov z1.d, #1 // =0x1
-; CHECK-NEXT: mov z0.d, x0
-; CHECK-NEXT: mov z2.d, x8
-; CHECK-NEXT: ptrue p0.d
-; CHECK-NEXT: mla z0.d, p0/m, z2.d, z1.d
+; CHECK-NEXT: mov z0.d, x8
+; CHECK-NEXT: mov z1.d, x0
+; CHECK-NEXT: add z0.d, z1.d, z0.d
; CHECK-NEXT: ret
%idx = shufflevector <vscale x 2 x i64> insertelement (<vscale x 2 x i64> undef, i64 1, i32 0), <vscale x 2 x i64> zeroinitializer, <vscale x 2 x i32> zeroinitializer
%d = getelementptr <vscale x 2 x i64>, <vscale x 2 x i64>* %base, <vscale x 2 x i64> %idx
@@ -120,10 +118,8 @@
; CHECK-LABEL: scalable_of_scalable_2:
; CHECK: // %bb.0:
; CHECK-NEXT: rdvl x8, #1
-; CHECK-NEXT: mov z1.d, #1 // =0x1
-; CHECK-NEXT: mov z2.d, x8
-; CHECK-NEXT: ptrue p0.d
-; CHECK-NEXT: mla z0.d, p0/m, z2.d, z1.d
+; CHECK-NEXT: mov z1.d, x8
+; CHECK-NEXT: add z0.d, z0.d, z1.d
; CHECK-NEXT: ret
%idx = shufflevector <vscale x 2 x i64> insertelement (<vscale x 2 x i64> undef, i64 1, i32 0), <vscale x 2 x i64> zeroinitializer, <vscale x 2 x i32> zeroinitializer
%d = getelementptr <vscale x 2 x i64>, <vscale x 2 x <vscale x 2 x i64>*> %base, <vscale x 2 x i64> %idx
Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
===================================================================
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
@@ -139,6 +139,15 @@
//===----------------------------------------------------------------------===//
bool ISD::isConstantSplatVector(const SDNode *N, APInt &SplatVal) {
+ if (N->getOpcode() == ISD::SPLAT_VECTOR) {
+ unsigned EltSize =
+ N->getValueType(0).getVectorElementType().getSizeInBits();
+ if (auto *Op0 = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
+ SplatVal = Op0->getAPIntValue().truncOrSelf(EltSize);
+ return true;
+ }
+ }
+
auto *BV = dyn_cast<BuildVectorSDNode>(N);
if (!BV)
return false;
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