[llvm] 4f87d30 - [AMDGPU] Introduce and use isGFX10Plus. NFC.
Jay Foad via llvm-commits
llvm-commits at lists.llvm.org
Thu Nov 26 01:02:53 PST 2020
Author: Jay Foad
Date: 2020-11-26T09:02:36Z
New Revision: 4f87d30a06dd08cec45cb595e9dbed6345c9a7c5
URL: https://github.com/llvm/llvm-project/commit/4f87d30a06dd08cec45cb595e9dbed6345c9a7c5
DIFF: https://github.com/llvm/llvm-project/commit/4f87d30a06dd08cec45cb595e9dbed6345c9a7c5.diff
LOG: [AMDGPU] Introduce and use isGFX10Plus. NFC.
It's more future-proof to use isGFX10Plus from the start, on the
assumption that future architectures will be based on current
architectures.
Also make use of the existing isGFX9Plus in a few places.
Differential Revision: https://reviews.llvm.org/D92092
Added:
Modified:
llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp
llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.h
llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp
llvm/lib/Target/AMDGPU/MCTargetDesc/SIMCCodeEmitter.cpp
llvm/lib/Target/AMDGPU/SIISelLowering.cpp
llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
Removed:
################################################################################
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp b/llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp
index 8148d0487802..137f6896c87b 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp
@@ -338,7 +338,7 @@ bool AMDGPUAsmPrinter::doFinalization(Module &M) {
// causing stale data in caches. Arguably this should be done by the linker,
// which is why this isn't done for Mesa.
const MCSubtargetInfo &STI = *getGlobalSTI();
- if (AMDGPU::isGFX10(STI) &&
+ if (AMDGPU::isGFX10Plus(STI) &&
(STI.getTargetTriple().getOS() == Triple::AMDHSA ||
STI.getTargetTriple().getOS() == Triple::AMDPAL)) {
OutStreamer->SwitchSection(getObjFileLowering().getTextSection());
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp b/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
index 37a79ce4fa37..20b7c7849397 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
@@ -1485,7 +1485,7 @@ bool AMDGPUInstructionSelector::selectImageIntrinsic(
const AMDGPU::MIMGMIPMappingInfo *MIPMappingInfo =
AMDGPU::getMIMGMIPMappingInfo(Intr->BaseOpcode);
unsigned IntrOpcode = Intr->BaseOpcode;
- const bool IsGFX10 = STI.getGeneration() >= AMDGPUSubtarget::GFX10;
+ const bool IsGFX10Plus = AMDGPU::isGFX10Plus(STI);
const unsigned ArgOffset = MI.getNumExplicitDefs() + 1;
@@ -1603,12 +1603,12 @@ bool AMDGPUInstructionSelector::selectImageIntrinsic(
GLC = true; // TODO no-return optimization
if (!parseCachePolicy(
MI.getOperand(ArgOffset + Intr->CachePolicyIndex).getImm(), nullptr,
- &SLC, IsGFX10 ? &DLC : nullptr))
+ &SLC, IsGFX10Plus ? &DLC : nullptr))
return false;
} else {
if (!parseCachePolicy(
MI.getOperand(ArgOffset + Intr->CachePolicyIndex).getImm(), &GLC,
- &SLC, IsGFX10 ? &DLC : nullptr))
+ &SLC, IsGFX10Plus ? &DLC : nullptr))
return false;
}
@@ -1641,7 +1641,7 @@ bool AMDGPUInstructionSelector::selectImageIntrinsic(
++NumVDataDwords;
int Opcode = -1;
- if (IsGFX10) {
+ if (IsGFX10Plus) {
Opcode = AMDGPU::getMIMGOpcode(IntrOpcode,
UseNSA ? AMDGPU::MIMGEncGfx10NSA
: AMDGPU::MIMGEncGfx10Default,
@@ -1693,22 +1693,22 @@ bool AMDGPUInstructionSelector::selectImageIntrinsic(
MIB.addImm(DMask); // dmask
- if (IsGFX10)
+ if (IsGFX10Plus)
MIB.addImm(DimInfo->Encoding);
MIB.addImm(Unorm);
- if (IsGFX10)
+ if (IsGFX10Plus)
MIB.addImm(DLC);
MIB.addImm(GLC);
MIB.addImm(SLC);
MIB.addImm(IsA16 && // a16 or r128
STI.hasFeature(AMDGPU::FeatureR128A16) ? -1 : 0);
- if (IsGFX10)
+ if (IsGFX10Plus)
MIB.addImm(IsA16 ? -1 : 0);
MIB.addImm(TFE); // tfe
MIB.addImm(LWE); // lwe
- if (!IsGFX10)
+ if (!IsGFX10Plus)
MIB.addImm(DimInfo->DA ? -1 : 0);
if (BaseOpcode->HasD16)
MIB.addImm(IsD16 ? -1 : 0);
diff --git a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
index 4f05ba5ab576..b8b747ea8f99 100644
--- a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
+++ b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
@@ -1232,6 +1232,8 @@ class AMDGPUAsmParser : public MCTargetAsmParser {
return AMDGPU::isGFX10(getSTI());
}
+ bool isGFX10Plus() const { return AMDGPU::isGFX10Plus(getSTI()); }
+
bool isGFX10_BEncoding() const {
return AMDGPU::isGFX10_BEncoding(getSTI());
}
@@ -1248,9 +1250,7 @@ class AMDGPUAsmParser : public MCTargetAsmParser {
return !isVI() && !isGFX9();
}
- bool hasSGPR104_SGPR105() const {
- return isGFX10();
- }
+ bool hasSGPR104_SGPR105() const { return isGFX10Plus(); }
bool hasIntClamp() const {
return getFeatureBits()[AMDGPU::FeatureIntClamp];
@@ -1752,7 +1752,7 @@ bool AMDGPUOperand::isRegClass(unsigned RCID) const {
bool AMDGPUOperand::isSDWAOperand(MVT type) const {
if (AsmParser->isVI())
return isVReg32();
- else if (AsmParser->isGFX9() || AsmParser->isGFX10())
+ else if (AsmParser->isGFX9Plus())
return isRegClass(AMDGPU::VS_32RegClassID) || isInlinableImm(type);
else
return false;
@@ -3028,7 +3028,7 @@ bool AMDGPUAsmParser::isInlineConstant(const MCInst &Inst,
}
unsigned AMDGPUAsmParser::getConstantBusLimit(unsigned Opcode) const {
- if (!isGFX10())
+ if (!isGFX10Plus())
return 1;
switch (Opcode) {
@@ -3244,7 +3244,7 @@ bool AMDGPUAsmParser::validateMIMGAddrSize(const MCInst &Inst) {
const unsigned Opc = Inst.getOpcode();
const MCInstrDesc &Desc = MII.get(Opc);
- if ((Desc.TSFlags & SIInstrFlags::MIMG) == 0 || !isGFX10())
+ if ((Desc.TSFlags & SIInstrFlags::MIMG) == 0 || !isGFX10Plus())
return true;
const AMDGPU::MIMGInfo *Info = AMDGPU::getMIMGInfo(Opc);
@@ -4514,7 +4514,7 @@ bool AMDGPUAsmParser::ParseAMDKernelCodeTValue(StringRef ID,
if (ID == "enable_wavefront_size32") {
if (Header.code_properties & AMD_CODE_PROPERTY_ENABLE_WAVEFRONT_SIZE32) {
- if (!isGFX10())
+ if (!isGFX10Plus())
return TokError("enable_wavefront_size32=1 is only allowed on GFX10+");
if (!getFeatureBits()[AMDGPU::FeatureWavefrontSize32])
return TokError("enable_wavefront_size32=1 requires +WavefrontSize32");
@@ -4526,7 +4526,7 @@ bool AMDGPUAsmParser::ParseAMDKernelCodeTValue(StringRef ID,
if (ID == "wavefront_size") {
if (Header.wavefront_size == 5) {
- if (!isGFX10())
+ if (!isGFX10Plus())
return TokError("wavefront_size=5 is only allowed on GFX10+");
if (!getFeatureBits()[AMDGPU::FeatureWavefrontSize32])
return TokError("wavefront_size=5 requires +WavefrontSize32");
@@ -4537,17 +4537,20 @@ bool AMDGPUAsmParser::ParseAMDKernelCodeTValue(StringRef ID,
}
if (ID == "enable_wgp_mode") {
- if (G_00B848_WGP_MODE(Header.compute_pgm_resource_registers) && !isGFX10())
+ if (G_00B848_WGP_MODE(Header.compute_pgm_resource_registers) &&
+ !isGFX10Plus())
return TokError("enable_wgp_mode=1 is only allowed on GFX10+");
}
if (ID == "enable_mem_ordered") {
- if (G_00B848_MEM_ORDERED(Header.compute_pgm_resource_registers) && !isGFX10())
+ if (G_00B848_MEM_ORDERED(Header.compute_pgm_resource_registers) &&
+ !isGFX10Plus())
return TokError("enable_mem_ordered=1 is only allowed on GFX10+");
}
if (ID == "enable_fwd_progress") {
- if (G_00B848_FWD_PROGRESS(Header.compute_pgm_resource_registers) && !isGFX10())
+ if (G_00B848_FWD_PROGRESS(Header.compute_pgm_resource_registers) &&
+ !isGFX10Plus())
return TokError("enable_fwd_progress=1 is only allowed on GFX10+");
}
@@ -4870,13 +4873,13 @@ bool AMDGPUAsmParser::subtargetHasRegister(const MCRegisterInfo &MRI,
case AMDGPU::TMA:
case AMDGPU::TMA_LO:
case AMDGPU::TMA_HI:
- return !isGFX9() && !isGFX10();
+ return !isGFX9Plus();
case AMDGPU::XNACK_MASK:
case AMDGPU::XNACK_MASK_LO:
case AMDGPU::XNACK_MASK_HI:
- return !isCI() && !isSI() && !isGFX10() && hasXNACK();
+ return !isCI() && !isSI() && !isGFX10Plus() && hasXNACK();
case AMDGPU::SGPR_NULL:
- return isGFX10();
+ return isGFX10Plus();
default:
break;
}
@@ -4884,7 +4887,7 @@ bool AMDGPUAsmParser::subtargetHasRegister(const MCRegisterInfo &MRI,
if (isCI())
return true;
- if (isSI() || isGFX10()) {
+ if (isSI() || isGFX10Plus()) {
// No flat_scr on SI.
// On GFX10 flat scratch is not a valid register operand and can only be
// accessed with s_setreg/s_getreg.
@@ -4990,7 +4993,7 @@ bool AMDGPUAsmParser::ParseInstruction(ParseInstructionInfo &Info,
while (!getLexer().is(AsmToken::EndOfStatement)) {
OperandMode Mode = OperandMode_Default;
- if (IsMIMG && isGFX10() && Operands.size() == 2)
+ if (IsMIMG && isGFX10Plus() && Operands.size() == 2)
Mode = OperandMode_NSA;
OperandMatchResultTy Res = parseOperand(Operands, Name, Mode);
@@ -5127,7 +5130,7 @@ AMDGPUAsmParser::parseNamedBit(const char *Name, OperandVector &Operands,
}
}
- if (!isGFX10() && ImmTy == AMDGPUOperand::ImmTyDLC)
+ if (!isGFX10Plus() && ImmTy == AMDGPUOperand::ImmTyDLC)
return MatchOperand_ParseFail;
if (isGFX9() && ImmTy == AMDGPUOperand::ImmTyA16)
@@ -5304,7 +5307,7 @@ AMDGPUAsmParser::parseSymbolicSplitFormat(StringRef FormatStr,
Dfmt = (Dfmt == DFMT_UNDEF) ? DFMT_DEFAULT : Dfmt;
Nfmt = (Nfmt == NFMT_UNDEF) ? NFMT_DEFAULT : Nfmt;
- if (isGFX10()) {
+ if (isGFX10Plus()) {
auto Ufmt = convertDfmtNfmt2Ufmt(Dfmt, Nfmt);
if (Ufmt == UFMT_UNDEF) {
Error(FormatLoc, "unsupported format");
@@ -5328,7 +5331,7 @@ AMDGPUAsmParser::parseSymbolicUnifiedFormat(StringRef FormatStr,
if (Id == UFMT_UNDEF)
return MatchOperand_NoMatch;
- if (!isGFX10()) {
+ if (!isGFX10Plus()) {
Error(Loc, "unified format is not supported on this GPU");
return MatchOperand_ParseFail;
}
@@ -5389,7 +5392,7 @@ AMDGPUAsmParser::parseFORMAT(OperandVector &Operands) {
SMLoc Loc = getLoc();
// Parse legacy format syntax.
- Res = isGFX10() ? parseUfmt(Format) : parseDfmtNfmt(Format);
+ Res = isGFX10Plus() ? parseUfmt(Format) : parseDfmtNfmt(Format);
if (Res == MatchOperand_ParseFail)
return Res;
@@ -5968,14 +5971,14 @@ OperandMatchResultTy AMDGPUAsmParser::parseExpTgtImpl(StringRef Str,
if (Str.getAsInteger(10, Val))
return MatchOperand_ParseFail;
- if (Val > (isGFX10() ? 4 : 3))
+ if (Val > (isGFX10Plus() ? 4 : 3))
return MatchOperand_ParseFail;
Val += Exp::ET_POS0;
return MatchOperand_Success;
}
- if (isGFX10() && Str == "prim") {
+ if (isGFX10Plus() && Str == "prim") {
Val = Exp::ET_PRIM;
return MatchOperand_Success;
}
@@ -6674,7 +6677,7 @@ void AMDGPUAsmParser::cvtMubufImpl(MCInst &Inst,
addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyTFE);
}
- if (isGFX10())
+ if (isGFX10Plus())
addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyDLC);
}
@@ -6714,7 +6717,7 @@ void AMDGPUAsmParser::cvtMtbuf(MCInst &Inst, const OperandVector &Operands) {
addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTySLC);
addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyTFE);
- if (isGFX10())
+ if (isGFX10Plus())
addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyDLC);
}
@@ -6751,22 +6754,22 @@ void AMDGPUAsmParser::cvtMIMG(MCInst &Inst, const OperandVector &Operands,
}
}
- bool IsGFX10 = isGFX10();
+ bool IsGFX10Plus = isGFX10Plus();
addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyDMask);
- if (IsGFX10)
+ if (IsGFX10Plus)
addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyDim, -1);
addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyUNorm);
- if (IsGFX10)
+ if (IsGFX10Plus)
addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyDLC);
addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyGLC);
addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTySLC);
addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyR128A16);
- if (IsGFX10)
+ if (IsGFX10Plus)
addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyA16);
addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyTFE);
addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyLWE);
- if (!IsGFX10)
+ if (!IsGFX10Plus)
addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyDA);
addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyD16);
}
@@ -7267,7 +7270,7 @@ bool AMDGPUOperand::isU16Imm() const {
}
OperandMatchResultTy AMDGPUAsmParser::parseDim(OperandVector &Operands) {
- if (!isGFX10())
+ if (!isGFX10Plus())
return MatchOperand_NoMatch;
SMLoc S = Parser.getTok().getLoc();
@@ -7324,7 +7327,7 @@ OperandMatchResultTy AMDGPUAsmParser::parseDPP8(OperandVector &Operands) {
if (Prefix != "dpp8")
return parseDPPCtrl(Operands);
- if (!isGFX10())
+ if (!isGFX10Plus())
return MatchOperand_NoMatch;
// dpp8:[%d,%d,%d,%d,%d,%d,%d,%d]
@@ -7404,7 +7407,7 @@ AMDGPUAsmParser::parseDPPCtrl(OperandVector &Operands) {
return MatchOperand_NoMatch;
}
- if (!isGFX10() && (Prefix == "row_share" || Prefix == "row_xmask"))
+ if (!isGFX10Plus() && (Prefix == "row_share" || Prefix == "row_xmask"))
return MatchOperand_NoMatch;
if (!isVI() && !isGFX9() &&
diff --git a/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp b/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
index 4907f325932d..adc635d2cf4a 100644
--- a/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
+++ b/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
@@ -52,8 +52,9 @@ using namespace llvm;
#define DEBUG_TYPE "amdgpu-disassembler"
-#define SGPR_MAX (isGFX10() ? AMDGPU::EncValues::SGPR_MAX_GFX10 \
- : AMDGPU::EncValues::SGPR_MAX_SI)
+#define SGPR_MAX \
+ (isGFX10Plus() ? AMDGPU::EncValues::SGPR_MAX_GFX10 \
+ : AMDGPU::EncValues::SGPR_MAX_SI)
using DecodeStatus = llvm::MCDisassembler::DecodeStatus;
@@ -64,7 +65,7 @@ AMDGPUDisassembler::AMDGPUDisassembler(const MCSubtargetInfo &STI,
TargetMaxInstBytes(Ctx.getAsmInfo()->getMaxInstLength(&STI)) {
// ToDo: AMDGPUDisassembler supports only VI ISA.
- if (!STI.getFeatureBits()[AMDGPU::FeatureGCN3Encoding] && !isGFX10())
+ if (!STI.getFeatureBits()[AMDGPU::FeatureGCN3Encoding] && !isGFX10Plus())
report_fatal_error("Disassembly not yet supported for subtarget");
}
@@ -1016,10 +1017,8 @@ unsigned AMDGPUDisassembler::getTtmpClassId(const OpWidthTy Width) const {
int AMDGPUDisassembler::getTTmpIdx(unsigned Val) const {
using namespace AMDGPU::EncValues;
- unsigned TTmpMin =
- (isGFX9() || isGFX10()) ? TTMP_GFX9_GFX10_MIN : TTMP_VI_MIN;
- unsigned TTmpMax =
- (isGFX9() || isGFX10()) ? TTMP_GFX9_GFX10_MAX : TTMP_VI_MAX;
+ unsigned TTmpMin = isGFX9Plus() ? TTMP_GFX9_GFX10_MIN : TTMP_VI_MIN;
+ unsigned TTmpMax = isGFX9Plus() ? TTMP_GFX9_GFX10_MAX : TTMP_VI_MAX;
return (TTmpMin <= Val && Val <= TTmpMax)? Val - TTmpMin : -1;
}
@@ -1157,8 +1156,8 @@ MCOperand AMDGPUDisassembler::decodeSDWASrc(const OpWidthTy Width,
Val - SDWA9EncValues::SRC_VGPR_MIN);
}
if (SDWA9EncValues::SRC_SGPR_MIN <= Val &&
- Val <= (isGFX10() ? SDWA9EncValues::SRC_SGPR_MAX_GFX10
- : SDWA9EncValues::SRC_SGPR_MAX_SI)) {
+ Val <= (isGFX10Plus() ? SDWA9EncValues::SRC_SGPR_MAX_GFX10
+ : SDWA9EncValues::SRC_SGPR_MAX_SI)) {
return createSRegOperand(getSgprClassId(Width),
Val - SDWA9EncValues::SRC_SGPR_MIN);
}
@@ -1227,12 +1226,14 @@ bool AMDGPUDisassembler::isVI() const {
return STI.getFeatureBits()[AMDGPU::FeatureVolcanicIslands];
}
-bool AMDGPUDisassembler::isGFX9() const {
- return STI.getFeatureBits()[AMDGPU::FeatureGFX9];
-}
+bool AMDGPUDisassembler::isGFX9() const { return AMDGPU::isGFX9(STI); }
+
+bool AMDGPUDisassembler::isGFX9Plus() const { return AMDGPU::isGFX9Plus(STI); }
+
+bool AMDGPUDisassembler::isGFX10() const { return AMDGPU::isGFX10(STI); }
-bool AMDGPUDisassembler::isGFX10() const {
- return STI.getFeatureBits()[AMDGPU::FeatureGFX10];
+bool AMDGPUDisassembler::isGFX10Plus() const {
+ return AMDGPU::isGFX10Plus(STI);
}
//===----------------------------------------------------------------------===//
@@ -1287,7 +1288,7 @@ MCDisassembler::DecodeStatus AMDGPUDisassembler::decodeCOMPUTE_PGM_RSRC1(
(FourByteBuffer & COMPUTE_PGM_RSRC1_GRANULATED_WAVEFRONT_SGPR_COUNT) >>
COMPUTE_PGM_RSRC1_GRANULATED_WAVEFRONT_SGPR_COUNT_SHIFT;
- if (isGFX10() && GranulatedWavefrontSGPRCount)
+ if (isGFX10Plus() && GranulatedWavefrontSGPRCount)
return MCDisassembler::Fail;
uint32_t NextFreeSGPR = (GranulatedWavefrontSGPRCount + 1) *
@@ -1331,7 +1332,7 @@ MCDisassembler::DecodeStatus AMDGPUDisassembler::decodeCOMPUTE_PGM_RSRC1(
if (FourByteBuffer & COMPUTE_PGM_RSRC1_RESERVED0)
return MCDisassembler::Fail;
- if (isGFX10()) {
+ if (isGFX10Plus()) {
PRINT_DIRECTIVE(".amdhsa_workgroup_processor_mode",
COMPUTE_PGM_RSRC1_WGP_MODE);
PRINT_DIRECTIVE(".amdhsa_memory_ordered", COMPUTE_PGM_RSRC1_MEM_ORDERED);
@@ -1456,7 +1457,7 @@ AMDGPUDisassembler::decodeKernelDescriptorDirective(
// - Only set for GFX10, GFX6-9 have this to be 0.
// - Currently no directives directly control this.
FourByteBuffer = DE.getU32(Cursor);
- if (!isGFX10() && FourByteBuffer) {
+ if (!isGFX10Plus() && FourByteBuffer) {
return MCDisassembler::Fail;
}
return MCDisassembler::Success;
@@ -1503,7 +1504,7 @@ AMDGPUDisassembler::decodeKernelDescriptorDirective(
if (isGFX9() &&
(TwoByteBuffer & KERNEL_CODE_PROPERTY_ENABLE_WAVEFRONT_SIZE32)) {
return MCDisassembler::Fail;
- } else if (isGFX10()) {
+ } else if (isGFX10Plus()) {
PRINT_DIRECTIVE(".amdhsa_wavefront_size32",
KERNEL_CODE_PROPERTY_ENABLE_WAVEFRONT_SIZE32);
}
diff --git a/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.h b/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.h
index 315602c35288..34a1eb019c61 100644
--- a/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.h
+++ b/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.h
@@ -168,7 +168,9 @@ class AMDGPUDisassembler : public MCDisassembler {
bool isVI() const;
bool isGFX9() const;
+ bool isGFX9Plus() const;
bool isGFX10() const;
+ bool isGFX10Plus() const;
};
//===----------------------------------------------------------------------===//
diff --git a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp
index dc9c54e4aaac..73cd9b9a8174 100644
--- a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp
+++ b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp
@@ -155,7 +155,7 @@ void AMDGPUInstPrinter::printFlatOffset(const MCInst *MI, unsigned OpNo,
if (IsFlatSeg) { // Unsigned offset
printU16ImmDecOperand(MI, OpNo, O);
} else { // Signed offset
- if (AMDGPU::isGFX10(STI)) {
+ if (AMDGPU::isGFX10Plus(STI)) {
O << formatDec(SignExtend32<12>(MI->getOperand(OpNo).getImm()));
} else {
O << formatDec(SignExtend32<13>(MI->getOperand(OpNo).getImm()));
@@ -207,7 +207,7 @@ void AMDGPUInstPrinter::printGDS(const MCInst *MI, unsigned OpNo,
void AMDGPUInstPrinter::printDLC(const MCInst *MI, unsigned OpNo,
const MCSubtargetInfo &STI, raw_ostream &O) {
- if (AMDGPU::isGFX10(STI))
+ if (AMDGPU::isGFX10Plus(STI))
printNamedBit(MI, OpNo, O, "dlc");
}
@@ -310,7 +310,7 @@ void AMDGPUInstPrinter::printSymbolicFormat(const MCInst *MI,
assert(OpNo != -1);
unsigned Val = MI->getOperand(OpNo).getImm();
- if (AMDGPU::isGFX10(STI)) {
+ if (AMDGPU::isGFX10Plus(STI)) {
if (Val == UFMT_DEFAULT)
return;
if (isValidUnifiedFormat(Val)) {
@@ -780,7 +780,7 @@ void AMDGPUInstPrinter::printOperandAndIntInputMods(const MCInst *MI,
void AMDGPUInstPrinter::printDPP8(const MCInst *MI, unsigned OpNo,
const MCSubtargetInfo &STI,
raw_ostream &O) {
- if (!AMDGPU::isGFX10(STI))
+ if (!AMDGPU::isGFX10Plus(STI))
llvm_unreachable("dpp8 is not supported on ASICs earlier than GFX10");
unsigned Imm = MI->getOperand(OpNo).getImm();
@@ -816,25 +816,25 @@ void AMDGPUInstPrinter::printDPPCtrl(const MCInst *MI, unsigned OpNo,
O << "row_ror:";
printU4ImmDecOperand(MI, OpNo, O);
} else if (Imm == DppCtrl::WAVE_SHL1) {
- if (!AMDGPU::isVI(STI) && !AMDGPU::isGFX9(STI)) {
+ if (AMDGPU::isGFX10Plus(STI)) {
O << "/* wave_shl is not supported starting from GFX10 */";
return;
}
O << "wave_shl:1";
} else if (Imm == DppCtrl::WAVE_ROL1) {
- if (!AMDGPU::isVI(STI) && !AMDGPU::isGFX9(STI)) {
+ if (AMDGPU::isGFX10Plus(STI)) {
O << "/* wave_rol is not supported starting from GFX10 */";
return;
}
O << "wave_rol:1";
} else if (Imm == DppCtrl::WAVE_SHR1) {
- if (!AMDGPU::isVI(STI) && !AMDGPU::isGFX9(STI)) {
+ if (AMDGPU::isGFX10Plus(STI)) {
O << "/* wave_shr is not supported starting from GFX10 */";
return;
}
O << "wave_shr:1";
} else if (Imm == DppCtrl::WAVE_ROR1) {
- if (!AMDGPU::isVI(STI) && !AMDGPU::isGFX9(STI)) {
+ if (AMDGPU::isGFX10Plus(STI)) {
O << "/* wave_ror is not supported starting from GFX10 */";
return;
}
@@ -844,20 +844,20 @@ void AMDGPUInstPrinter::printDPPCtrl(const MCInst *MI, unsigned OpNo,
} else if (Imm == DppCtrl::ROW_HALF_MIRROR) {
O << "row_half_mirror";
} else if (Imm == DppCtrl::BCAST15) {
- if (!AMDGPU::isVI(STI) && !AMDGPU::isGFX9(STI)) {
+ if (AMDGPU::isGFX10Plus(STI)) {
O << "/* row_bcast is not supported starting from GFX10 */";
return;
}
O << "row_bcast:15";
} else if (Imm == DppCtrl::BCAST31) {
- if (!AMDGPU::isVI(STI) && !AMDGPU::isGFX9(STI)) {
+ if (AMDGPU::isGFX10Plus(STI)) {
O << "/* row_bcast is not supported starting from GFX10 */";
return;
}
O << "row_bcast:31";
} else if ((Imm >= DppCtrl::ROW_SHARE_FIRST) &&
(Imm <= DppCtrl::ROW_SHARE_LAST)) {
- if (!AMDGPU::isGFX10(STI)) {
+ if (!AMDGPU::isGFX10Plus(STI)) {
O << "/* row_share is not supported on ASICs earlier than GFX10 */";
return;
}
@@ -865,7 +865,7 @@ void AMDGPUInstPrinter::printDPPCtrl(const MCInst *MI, unsigned OpNo,
printU4ImmDecOperand(MI, OpNo, O);
} else if ((Imm >= DppCtrl::ROW_XMASK_FIRST) &&
(Imm <= DppCtrl::ROW_XMASK_LAST)) {
- if (!AMDGPU::isGFX10(STI)) {
+ if (!AMDGPU::isGFX10Plus(STI)) {
O << "/* row_xmask is not supported on ASICs earlier than GFX10 */";
return;
}
@@ -1023,9 +1023,9 @@ void AMDGPUInstPrinter::printExpTgt(const MCInst *MI, unsigned OpNo,
else if (Tgt == Exp::ET_NULL)
O << " null";
else if (Tgt >= Exp::ET_POS0 &&
- Tgt <= uint32_t(isGFX10(STI) ? Exp::ET_POS4 : Exp::ET_POS3))
+ Tgt <= uint32_t(isGFX10Plus(STI) ? Exp::ET_POS4 : Exp::ET_POS3))
O << " pos" << Tgt - Exp::ET_POS0;
- else if (isGFX10(STI) && Tgt == Exp::ET_PRIM)
+ else if (isGFX10Plus(STI) && Tgt == Exp::ET_PRIM)
O << " prim";
else if (Tgt >= Exp::ET_PARAM0 && Tgt <= Exp::ET_PARAM31)
O << " param" << Tgt - Exp::ET_PARAM0;
diff --git a/llvm/lib/Target/AMDGPU/MCTargetDesc/SIMCCodeEmitter.cpp b/llvm/lib/Target/AMDGPU/MCTargetDesc/SIMCCodeEmitter.cpp
index 2cd6c3a81d2b..6226e6026740 100644
--- a/llvm/lib/Target/AMDGPU/MCTargetDesc/SIMCCodeEmitter.cpp
+++ b/llvm/lib/Target/AMDGPU/MCTargetDesc/SIMCCodeEmitter.cpp
@@ -303,7 +303,7 @@ void SIMCCodeEmitter::encodeInstruction(const MCInst &MI, raw_ostream &OS,
}
// NSA encoding.
- if (AMDGPU::isGFX10(STI) && Desc.TSFlags & SIInstrFlags::MIMG) {
+ if (AMDGPU::isGFX10Plus(STI) && Desc.TSFlags & SIInstrFlags::MIMG) {
int vaddr0 = AMDGPU::getNamedOperandIdx(MI.getOpcode(),
AMDGPU::OpName::vaddr0);
int srsrc = AMDGPU::getNamedOperandIdx(MI.getOpcode(),
diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
index 26b2150703e3..8f74a2ee14bf 100644
--- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
@@ -5987,7 +5987,7 @@ SDValue SITargetLowering::lowerImage(SDValue Op,
const AMDGPU::MIMGMIPMappingInfo *MIPMappingInfo =
AMDGPU::getMIMGMIPMappingInfo(Intr->BaseOpcode);
unsigned IntrOpcode = Intr->BaseOpcode;
- bool IsGFX10 = Subtarget->getGeneration() >= AMDGPUSubtarget::GFX10;
+ bool IsGFX10Plus = AMDGPU::isGFX10Plus(*Subtarget);
SmallVector<EVT, 3> ResultTypes(Op->value_begin(), Op->value_end());
SmallVector<EVT, 3> OrigResultTypes(Op->value_begin(), Op->value_end());
@@ -6235,11 +6235,11 @@ SDValue SITargetLowering::lowerImage(SDValue Op,
if (BaseOpcode->Atomic) {
GLC = True; // TODO no-return optimization
if (!parseCachePolicy(Op.getOperand(ArgOffset + Intr->CachePolicyIndex),
- DAG, nullptr, &SLC, IsGFX10 ? &DLC : nullptr))
+ DAG, nullptr, &SLC, IsGFX10Plus ? &DLC : nullptr))
return Op;
} else {
if (!parseCachePolicy(Op.getOperand(ArgOffset + Intr->CachePolicyIndex),
- DAG, &GLC, &SLC, IsGFX10 ? &DLC : nullptr))
+ DAG, &GLC, &SLC, IsGFX10Plus ? &DLC : nullptr))
return Op;
}
@@ -6256,20 +6256,20 @@ SDValue SITargetLowering::lowerImage(SDValue Op,
if (BaseOpcode->Sampler)
Ops.push_back(Op.getOperand(ArgOffset + Intr->SampIndex));
Ops.push_back(DAG.getTargetConstant(DMask, DL, MVT::i32));
- if (IsGFX10)
+ if (IsGFX10Plus)
Ops.push_back(DAG.getTargetConstant(DimInfo->Encoding, DL, MVT::i32));
Ops.push_back(Unorm);
- if (IsGFX10)
+ if (IsGFX10Plus)
Ops.push_back(DLC);
Ops.push_back(GLC);
Ops.push_back(SLC);
Ops.push_back(IsA16 && // r128, a16 for gfx9
ST->hasFeature(AMDGPU::FeatureR128A16) ? True : False);
- if (IsGFX10)
+ if (IsGFX10Plus)
Ops.push_back(IsA16 ? True : False);
Ops.push_back(TFE);
Ops.push_back(LWE);
- if (!IsGFX10)
+ if (!IsGFX10Plus)
Ops.push_back(DimInfo->DA ? True : False);
if (BaseOpcode->HasD16)
Ops.push_back(IsD16 ? True : False);
@@ -6280,7 +6280,7 @@ SDValue SITargetLowering::lowerImage(SDValue Op,
UseNSA ? VAddrs.size() : VAddr.getValueType().getSizeInBits() / 32;
int Opcode = -1;
- if (IsGFX10) {
+ if (IsGFX10Plus) {
Opcode = AMDGPU::getMIMGOpcode(IntrOpcode,
UseNSA ? AMDGPU::MIMGEncGfx10NSA
: AMDGPU::MIMGEncGfx10Default,
@@ -6559,11 +6559,11 @@ SDValue SITargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
return DAG.getConstant(MF.getSubtarget<GCNSubtarget>().getWavefrontSize(),
SDLoc(Op), MVT::i32);
case Intrinsic::amdgcn_s_buffer_load: {
- bool IsGFX10 = Subtarget->getGeneration() >= AMDGPUSubtarget::GFX10;
+ bool IsGFX10Plus = AMDGPU::isGFX10Plus(*Subtarget);
SDValue GLC;
SDValue DLC = DAG.getTargetConstant(0, DL, MVT::i1);
if (!parseCachePolicy(Op.getOperand(3), DAG, &GLC, nullptr,
- IsGFX10 ? &DLC : nullptr))
+ IsGFX10Plus ? &DLC : nullptr))
return Op;
return lowerSBuffer(VT, DL, Op.getOperand(1), Op.getOperand(2), Op.getOperand(3),
DAG);
diff --git a/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp b/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
index cd824a17750e..8193eedf391d 100644
--- a/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
@@ -310,7 +310,7 @@ unsigned getEUsPerCU(const MCSubtargetInfo *STI) {
// "Per CU" really means "per whatever functional block the waves of a
// workgroup must share". For gfx10 in CU mode this is the CU, which contains
// two SIMDs.
- if (isGFX10(*STI) && STI->getFeatureBits().test(FeatureCuMode))
+ if (isGFX10Plus(*STI) && STI->getFeatureBits().test(FeatureCuMode))
return 2;
// Pre-gfx10 a CU contains four SIMDs. For gfx10 in WGP mode the WGP contains
// two CUs, so a total of four SIMDs.
@@ -335,7 +335,7 @@ unsigned getMinWavesPerEU(const MCSubtargetInfo *STI) {
unsigned getMaxWavesPerEU(const MCSubtargetInfo *STI) {
// FIXME: Need to take scratch memory into account.
- if (!isGFX10(*STI))
+ if (!isGFX10Plus(*STI))
return 10;
return hasGFX10_3Insts(*STI) ? 16 : 20;
}
@@ -485,7 +485,7 @@ unsigned getVGPREncodingGranule(const MCSubtargetInfo *STI,
}
unsigned getTotalNumVGPRs(const MCSubtargetInfo *STI) {
- if (!isGFX10(*STI))
+ if (!isGFX10Plus(*STI))
return 256;
return STI->getFeatureBits().test(FeatureWavefrontSize32) ? 1024 : 512;
}
@@ -896,11 +896,11 @@ int64_t convertDfmtNfmt2Ufmt(unsigned Dfmt, unsigned Nfmt) {
}
bool isValidFormatEncoding(unsigned Val, const MCSubtargetInfo &STI) {
- return isGFX10(STI) ? (Val <= UFMT_MAX) : (Val <= DFMT_NFMT_MAX);
+ return isGFX10Plus(STI) ? (Val <= UFMT_MAX) : (Val <= DFMT_NFMT_MAX);
}
unsigned getDefaultFormatEncoding(const MCSubtargetInfo &STI) {
- if (isGFX10(STI))
+ if (isGFX10Plus(STI))
return UFMT_DEFAULT;
return DFMT_NFMT_DEFAULT;
}
@@ -928,7 +928,7 @@ static bool isValidMsgId(int64_t MsgId) {
bool isValidMsgId(int64_t MsgId, const MCSubtargetInfo &STI, bool Strict) {
if (Strict) {
if (MsgId == ID_GS_ALLOC_REQ || MsgId == ID_GET_DOORBELL)
- return isGFX9(STI) || isGFX10(STI);
+ return isGFX9Plus(STI);
else
return isValidMsgId(MsgId);
} else {
@@ -1109,13 +1109,15 @@ bool isGFX9(const MCSubtargetInfo &STI) {
}
bool isGFX9Plus(const MCSubtargetInfo &STI) {
- return isGFX9(STI) || isGFX10(STI);
+ return isGFX9(STI) || isGFX10Plus(STI);
}
bool isGFX10(const MCSubtargetInfo &STI) {
return STI.getFeatureBits()[AMDGPU::FeatureGFX10];
}
+bool isGFX10Plus(const MCSubtargetInfo &STI) { return isGFX10(STI); }
+
bool isGCN3Encoding(const MCSubtargetInfo &STI) {
return STI.getFeatureBits()[AMDGPU::FeatureGCN3Encoding];
}
@@ -1455,11 +1457,11 @@ bool isArgPassedInSGPR(const Argument *A) {
}
static bool hasSMEMByteOffset(const MCSubtargetInfo &ST) {
- return isGCN3Encoding(ST) || isGFX10(ST);
+ return isGCN3Encoding(ST) || isGFX10Plus(ST);
}
static bool hasSMRDSignedImmOffset(const MCSubtargetInfo &ST) {
- return isGFX9(ST) || isGFX10(ST);
+ return isGFX9Plus(ST);
}
bool isLegalSMRDEncodedUnsignedOffset(const MCSubtargetInfo &ST,
@@ -1616,7 +1618,7 @@ const GcnBufferFormatInfo *getGcnBufferFormatInfo(uint8_t BitsPerComp,
uint8_t NumComponents,
uint8_t NumFormat,
const MCSubtargetInfo &STI) {
- return isGFX10(STI)
+ return isGFX10Plus(STI)
? getGfx10PlusBufferFormatInfo(BitsPerComp, NumComponents,
NumFormat)
: getGfx9BufferFormatInfo(BitsPerComp, NumComponents, NumFormat);
@@ -1624,8 +1626,8 @@ const GcnBufferFormatInfo *getGcnBufferFormatInfo(uint8_t BitsPerComp,
const GcnBufferFormatInfo *getGcnBufferFormatInfo(uint8_t Format,
const MCSubtargetInfo &STI) {
- return isGFX10(STI) ? getGfx10PlusBufferFormatInfo(Format)
- : getGfx9BufferFormatInfo(Format);
+ return isGFX10Plus(STI) ? getGfx10PlusBufferFormatInfo(Format)
+ : getGfx9BufferFormatInfo(Format);
}
} // namespace AMDGPU
diff --git a/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h b/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
index e3cb4aa9641e..7afc1bca670c 100644
--- a/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
+++ b/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
@@ -601,6 +601,7 @@ bool isVI(const MCSubtargetInfo &STI);
bool isGFX9(const MCSubtargetInfo &STI);
bool isGFX9Plus(const MCSubtargetInfo &STI);
bool isGFX10(const MCSubtargetInfo &STI);
+bool isGFX10Plus(const MCSubtargetInfo &STI);
bool isGCN3Encoding(const MCSubtargetInfo &STI);
bool isGFX10_BEncoding(const MCSubtargetInfo &STI);
bool hasGFX10_3Insts(const MCSubtargetInfo &STI);
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