[PATCH] D92147: [RISCV] Add support for printing pcrel immediates as absolute addresses in llvm-objdump

[Craig Topper via Phabricator via llvm-commits]

craig.topper created this revision.
craig.topper added reviewers: MaskRay, asb, lenary, luismarques, HsiangKai, evandro.
Herald added subscribers: frasercrmck, NickHung, apazos, sameer.abuasal, pzheng, s.egerton, Jim, benna, psnobl, jocewei, PkmX, the_o, brucehoult, MartinMosbeck, rogfer01, edward-jones, zzheng, shiva0217, kito-cheng, niosHD, sabuasal, simoncook, johnrusso, rbar, hiraditya, emaste.
Herald added a reviewer: espindola.
Herald added a project: LLVM.
craig.topper requested review of this revision.

This makes the llvm-objdump output much more readable and closer to binutils objdump. This builds on https://reviews.llvm.org/D76591

It requires changing the OperandType for certain immediates to "OPERAND_PCREL" so tablegen will generate code to pass the instruction's address. This means we can't do the generic check on these instructions in verifyInstruction any more. Should I add it back with explicit opcode checks? Or should we add a new operand flag to control the passing of address instead of matching the name?


https://reviews.llvm.org/D92147

Files:
  lld/test/ELF/riscv-branch.s
  lld/test/ELF/riscv-jal.s
  lld/test/ELF/riscv-undefined-weak.s
  llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp
  llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.h
  llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
  llvm/lib/Target/RISCV/RISCVInstrInfo.td
  llvm/lib/Target/RISCV/RISCVInstrInfoC.td
  llvm/lib/Target/RISCV/Utils/RISCVBaseInfo.h
  llvm/test/CodeGen/RISCV/compress.ll
  llvm/test/MC/Disassembler/RISCV/branch-targets.txt
  llvm/test/MC/RISCV/compress-cjal.s
  llvm/test/MC/RISCV/compress-rv32i.s
  llvm/test/MC/RISCV/fixups-compressed.s
  llvm/test/MC/RISCV/fixups.s
  llvm/test/MC/RISCV/rv32-relaxation.s
  llvm/test/MC/RISCV/rv32c-only-valid.s
  llvm/test/MC/RISCV/rv32c-valid.s
  llvm/test/MC/RISCV/rv32e-valid.s
  llvm/test/MC/RISCV/rv32i-valid.s
  llvm/test/MC/RISCV/rv64-relax-all.s
  llvm/test/MC/RISCV/rv64-relaxation.s
  llvm/test/MC/RISCV/rvi-aliases-valid.s
  llvm/test/MC/RISCV/rvv/snippet.s

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