[PATCH] D90738: [RISCV] Support Zfh half-precision floating-point extension.
Jessica Clarke via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Wed Nov 25 16:07:32 PST 2020
jrtc27 requested changes to this revision.
jrtc27 added inline comments.
This revision now requires changes to proceed.
================
Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:1838-1843
+ // UseGPRForF16 if targeting one of the soft-float ABIs, if passing a
+ // variadic argument, or if no F16 argument registers are available.
+ bool UseGPRForF16 = true;
// UseGPRForF32 if targeting one of the soft-float ABIs, if passing a
// variadic argument, or if no F32 argument registers are available.
bool UseGPRForF32 = true;
----------------
jrtc27 wrote:
> These two are always the same value (unless you want an RV16I!), just rename the F32 one to encompass F16.
This comment still applies.
================
Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:1867-1872
+ if (State.getFirstUnallocated(ArgFPR16s) == array_lengthof(ArgFPR16s))
+ UseGPRForF16 = true;
if (State.getFirstUnallocated(ArgFPR32s) == array_lengthof(ArgFPR32s))
UseGPRForF32 = true;
if (State.getFirstUnallocated(ArgFPR64s) == array_lengthof(ArgFPR64s))
UseGPRForF64 = true;
----------------
jrtc27 wrote:
> Hm, this code is a bit silly, we only need to look at one of the arrays as the registers all alias each other.
Ditto
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D90738/new/
https://reviews.llvm.org/D90738
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