[PATCH] D90156: [PowerPC] Do not fold `cmp(d|w)` and `subf` instruction to `subf.` if `nsw` is not present

[Kai Luo via Phabricator via llvm-commits]

lkail updated this revision to Diff 307509.
lkail added a comment.

Rebased.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D90156/new/

https://reviews.llvm.org/D90156

Files:
  llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
  llvm/test/CodeGen/PowerPC/pr47830.ll


Index: llvm/test/CodeGen/PowerPC/pr47830.ll
===================================================================
--- llvm/test/CodeGen/PowerPC/pr47830.ll
+++ llvm/test/CodeGen/PowerPC/pr47830.ll
@@ -5,8 +5,9 @@
 define i64 @f(i64 %a, i64 %b) {
 ; CHECK-LABEL: f:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    sub. r3, r3, r4
-; CHECK-NEXT:    isellt r3, 0, r3
+; CHECK-NEXT:    sub r5, r3, r4
+; CHECK-NEXT:    cmpd r3, r4
+; CHECK-NEXT:    isellt r3, 0, r5
 ; CHECK-NEXT:    blr
   %c = icmp slt i64 %a, %b
   %d = sub i64 %a, %b
Index: llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
===================================================================
--- llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
+++ llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
@@ -2128,6 +2128,12 @@
   if (NewOpC == -1)
     return false;
 
+  // This transformation should not be performed if `nsw` is missing. Since if
+  // there is overflow, CR bits do not reflect correct order.
+  if (!equalityOnly && (NewOpC == PPC::SUBF_rec || NewOpC == PPC::SUBF8_rec) &&
+      Sub && !Sub->getFlag(MachineInstr::NoSWrap))
+    return false;
+
   // If we have SUB(r1, r2) and CMP(r2, r1), the condition code based on CMP
   // needs to be updated to be based on SUB.  Push the condition code
   // operands to OperandsToUpdate.  If it is safe to remove CmpInstr, the


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