[PATCH] D92071: [PowerPC] support register pressure reduction in machine combiner.

[ChenZheng via Phabricator via llvm-commits]

shchenz created this revision.
shchenz added reviewers: jsji, nemanjai, steven.zhang, PowerPC.
Herald added subscribers: llvm-commits, kbarton, hiraditya.
Herald added a project: LLVM.
shchenz requested review of this revision.

This patch tries to transform following patterns:

  // Pattern 1:
  //   A = FSUB  X,    Y        (Leaf)
  //   C = FMA   A31,  M31,  A  (Root)
  // M31 is const -->
  //   A = FMA   A31,  Y,  -M31
  //   C = FMA   A,    X,  M31
  //
  // Pattern 2:
  //   A = FSUB  X,    Y        (Leaf)
  //   C = FMA   A31,  A,  M32  (Root)
  // M32 is const -->
  //   A = FMA   A31,  Y,  -M32
  //   C = FMA   A,    X,  M32
  //
  // Pattern 3:
  //   A = FSUB  X,    Y        (Leaf)
  //   C = FMA   A31,  A,  M32  (Root)
  // Y is const -->
  //   A = FMA   A31,  -Y,  M32
  //   C = FMA   A,    X,   M32
  //
  // Pattern 4:
  //   A = FSUB  X,    Y        (Leaf)
  //   C = FMA   A31,  M31,  A  (Root)
  // Y is const -->
  //   A = FMA   A31,  -Y,  M31
  //   C = FMA   A,    X,   M31

On PowerPC target, fma instructions are destructive, its def is always assigned with the same physical register with one of its operands. We could use this characteristic to generate more fma instructions to generate friendly code for register allocation.

For example, for the below case:

  T = A * B + Const1 * (C - D) + Const2 * (E - F)

Without this patch, llvm generates:

  t0 = mul A, B
  t1 = sub C, D
  t2 = sub E, F
  ....
  t3 = FMA t0, Const1, t1
  T = FMA t3, Const2, t2

`t0` & `t1` & `t2` must be assigned with different registers.
With this patch, we get

  t0 = mul A, B
  t1 = FMA t0, Const1, C
  t2 = FMA t1, -Const1, D
  t3 = FMA t2, Const2, E
  T = FMA t3, -Const2, F

Now, `t0` & `t1` & `t2` & `t3` & `T` must be assigned with same physical register.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D92071

Files:
  llvm/include/llvm/CodeGen/MachineCombinerPattern.h
  llvm/lib/CodeGen/MachineCombiner.cpp
  llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
  llvm/lib/Target/PowerPC/PPCInstrInfo.h
  llvm/test/CodeGen/PowerPC/register-pressure-reduction.ll

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