[PATCH] D92068: [MachineCombiner] Add MustReduceRegisterPressure goal

[ChenZheng via Phabricator via llvm-commits]

shchenz created this revision.
shchenz added reviewers: spatel, eli.friedman, jsji, qcolombet, fhahn, steven.zhang.
Herald added subscribers: llvm-commits, nikic, pengfei, kbarton, hiraditya, nemanjai.
Herald added a project: LLVM.
shchenz requested review of this revision.

add a new goal MustReduceRegisterPressure for machine combiner pass.

This patch should be NFC except for pass pipeline changes. But after I add `LiveIntervals` analysis to this pass, it impacts several cases related to kill/dead flag. I have updated them accordingly. 
The strange change is the case `CodeGen/X86/coalescer-dce.ll`, it meets a verify error.

  *** Bad machine code: Virtual register defs don't dominate all uses. ***
  - function:    f1
  - v. register: %3

I think there must be some X86 specific bug, since I am not familiar with X86 target, I currently mark it as XFAIL. I will continue to investigate the reason.

PowerPC will use this new goal to do some register pressure related optimization. I will post that patch later.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D92068

Files:
  llvm/include/llvm/CodeGen/TargetInstrInfo.h
  llvm/lib/CodeGen/MachineCombiner.cpp
  llvm/lib/CodeGen/TargetInstrInfo.cpp
  llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
  llvm/lib/Target/AArch64/AArch64InstrInfo.h
  llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
  llvm/lib/Target/PowerPC/PPCInstrInfo.h
  llvm/test/CodeGen/AArch64/O3-pipeline.ll
  llvm/test/CodeGen/AArch64/aarch64-combine-fmul-fsub.mir
  llvm/test/CodeGen/AArch64/machine-combiner-instr-fmf.mir
  llvm/test/CodeGen/PowerPC/opt-cmp-inst-cr0-live.ll
  llvm/test/CodeGen/X86/coalescer-dce.ll
  llvm/test/CodeGen/X86/opt-pipeline.ll
  llvm/test/DebugInfo/X86/machinecse-wrongdebug-hoist.ll

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