[llvm] 4f5355e - [PowerPC] Don't reuse an illegal typed load for int_to_fp conversion.

[Sean Fertile via llvm-commits]

Author: Sean Fertile
Date: 2020-11-24T15:45:33-05:00
New Revision: 4f5355ee73626f8b8fe6bf0dd6d167fea7628a2c

URL: https://github.com/llvm/llvm-project/commit/4f5355ee73626f8b8fe6bf0dd6d167fea7628a2c
DIFF: https://github.com/llvm/llvm-project/commit/4f5355ee73626f8b8fe6bf0dd6d167fea7628a2c.diff

LOG: [PowerPC] Don't reuse an illegal typed load for int_to_fp conversion.

When the operand to an (s/u)int_to_fp node is an illegally typed load we
cannot reuse the load address since we can not build a proper dependancy
chain. The legalized loads will use a different chain output then the
illegal load. If we reuse the load address then we will build a
conversion node that uses the chain of the illegal load and operations
which modify the memory address in the other dependancy chain can be
scheduled before the floating point load which feeds the conversion.

Differential Revision: https://reviews.llvm.org/D91265

Added: 
    llvm/test/CodeGen/PowerPC/cvt_i64_to_fp.ll

Modified: 
    llvm/lib/Target/PowerPC/PPCISelLowering.cpp

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
index 4800b3391b98..ab74024158b0 100644
--- a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
+++ b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
@@ -8413,6 +8413,13 @@ bool PPCTargetLowering::canReuseLoadAddress(SDValue Op, EVT MemVT,
   if (LD->getMemoryVT() != MemVT)
     return false;
 
+  // If the result of the load is an illegal type, then we can't build a
+  // valid chain for reuse since the legalised loads and token factor node that
+  // ties the legalised loads together uses a 
diff erent output chain then the
+  // illegal load.
+  if (!isTypeLegal(LD->getValueType(0)))
+    return false;
+
   RLI.Ptr = LD->getBasePtr();
   if (LD->isIndexed() && !LD->getOffset().isUndef()) {
     assert(LD->getAddressingMode() == ISD::PRE_INC &&

diff  --git a/llvm/test/CodeGen/PowerPC/cvt_i64_to_fp.ll b/llvm/test/CodeGen/PowerPC/cvt_i64_to_fp.ll
new file mode 100644
index 000000000000..0bf8b47dbc63
--- /dev/null
+++ b/llvm/test/CodeGen/PowerPC/cvt_i64_to_fp.ll
@@ -0,0 +1,28 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN:  llc --verify-machineinstrs -mtriple powerpc-unknown-freebsd \
+; RUN:      -mcpu=pwr4 < %s | FileCheck %s
+
+define double @postinctodbl(i64* nocapture %llp) #0 {
+; CHECK-LABEL: postinctodbl:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    stwu 1, -16(1)
+; CHECK-NEXT:    .cfi_def_cfa_offset 16
+; CHECK-NEXT:    lwz 4, 4(3)
+; CHECK-NEXT:    stw 4, 12(1)
+; CHECK-NEXT:    addic 4, 4, 1
+; CHECK-NEXT:    lwz 5, 0(3)
+; CHECK-NEXT:    stw 5, 8(1)
+; CHECK-NEXT:    addze 5, 5
+; CHECK-NEXT:    lfd 0, 8(1)
+; CHECK-NEXT:    stw 5, 0(3)
+; CHECK-NEXT:    fcfid 1, 0
+; CHECK-NEXT:    stw 4, 4(3)
+; CHECK-NEXT:    addi 1, 1, 16
+; CHECK-NEXT:    blr
+entry:
+  %0 = load i64, i64* %llp, align 8
+  %inc = add nsw i64 %0, 1
+  store i64 %inc, i64* %llp, align 8
+  %conv = sitofp i64 %0 to double
+  ret double %conv
+}