[PATCH] D92029: [MC][ARM] Fix number of operands of tMOVSr

[Eugene Leviant via Phabricator via llvm-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rGa6a6d11c7b05: [MC][ARM] Fix number of operands of tMOVSr (authored by evgeny777).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D92029/new/

https://reviews.llvm.org/D92029

Files:
  llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
  llvm/test/MC/ARM/tMOVSr.s


Index: llvm/test/MC/ARM/tMOVSr.s
===================================================================
--- /dev/null
+++ llvm/test/MC/ARM/tMOVSr.s
@@ -0,0 +1,6 @@
+@ REQUIRES: asserts
+@ RUN: llvm-mc --triple=thumbv8 --debug %s 2>&1 | FileCheck %s --match-full-lines
+
+@ CHECK: Changed to: <MCInst #{{[0-9]+}} tMOVSr <MCOperand Reg:{{[0-9]+}}> <MCOperand Reg:{{[0-9]+}}>>
+.text
+  movs r2, r3
Index: llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
===================================================================
--- llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
+++ llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
@@ -10309,11 +10309,14 @@
         !HasWideQualifier) {
       // The operands aren't the same for tMOV[S]r... (no cc_out)
       MCInst TmpInst;
-      TmpInst.setOpcode(Inst.getOperand(4).getReg() ? ARM::tMOVSr : ARM::tMOVr);
+      unsigned Op = Inst.getOperand(4).getReg() ? ARM::tMOVSr : ARM::tMOVr;
+      TmpInst.setOpcode(Op);
       TmpInst.addOperand(Inst.getOperand(0));
       TmpInst.addOperand(Inst.getOperand(1));
-      TmpInst.addOperand(Inst.getOperand(2));
-      TmpInst.addOperand(Inst.getOperand(3));
+      if (Op == ARM::tMOVr) {
+        TmpInst.addOperand(Inst.getOperand(2));
+        TmpInst.addOperand(Inst.getOperand(3));
+      }
       Inst = TmpInst;
       return true;
     }


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